JPS5847945U - Request signal processing circuit - Google Patents

Request signal processing circuit

Info

Publication number
JPS5847945U
JPS5847945U JP14444381U JP14444381U JPS5847945U JP S5847945 U JPS5847945 U JP S5847945U JP 14444381 U JP14444381 U JP 14444381U JP 14444381 U JP14444381 U JP 14444381U JP S5847945 U JPS5847945 U JP S5847945U
Authority
JP
Japan
Prior art keywords
request signal
circuit
signal processing
processing circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14444381U
Other languages
Japanese (ja)
Inventor
砂田　力雄
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP14444381U priority Critical patent/JPS5847945U/en
Publication of JPS5847945U publication Critical patent/JPS5847945U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は、本考案の一実施例を示す電気的構成図である。 １〜４・・・記憶回路、０１〜Ｇ９・・・ゲート、５・
・・デコーダ、６・・・遅延回路、７・・・パルス発生
回路、８・・・レジスタ。　　−The figure is an electrical configuration diagram showing an embodiment of the present invention. 1-4...Memory circuit, 01-G9...Gate, 5.
...Decoder, 6...Delay circuit, 7...Pulse generation circuit, 8...Register. −

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 各要求信号を一時的に記憶する記憶回路と、各記憶回路
出力を同時に受けて要求信号の発生したルートのみ信号
を通すゲート回路と１．各デート回路を通過した信号を
受けるデコーダと、該デコーダ出力を一時的に記憶する
レジスタと、前記ゲート回路出力を受けて該レジスタへ
のデータ書込みパルスを出力するパルス発生回路とによ
り構成されてなる要求信号処理回路。1. A memory circuit that temporarily stores each request signal; a gate circuit that simultaneously receives the output of each memory circuit and passes the signal only through the route where the request signal is generated; 1. It is composed of a decoder that receives signals passed through each date circuit, a register that temporarily stores the output of the decoder, and a pulse generation circuit that receives the output of the gate circuit and outputs a data write pulse to the register. Request signal processing circuit.
JP14444381U 1981-09-29 1981-09-29 Request signal processing circuit Pending JPS5847945U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14444381U JPS5847945U (en) 1981-09-29 1981-09-29 Request signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14444381U JPS5847945U (en) 1981-09-29 1981-09-29 Request signal processing circuit

Publications (1)

Publication Number Publication Date
JPS5847945U true JPS5847945U (en) 1983-03-31

Family

ID=29937404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14444381U Pending JPS5847945U (en) 1981-09-29 1981-09-29 Request signal processing circuit

Country Status (1)

Country Link
JP (1) JPS5847945U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170700U (en) * 1984-04-19 1985-11-12 トリニテイ工業株式会社 flame monitoring window

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170700U (en) * 1984-04-19 1985-11-12 トリニテイ工業株式会社 flame monitoring window

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