JPS582048U - test equipment - Google Patents

test equipment

Info

Publication number
JPS582048U
JPS582048U JP9627581U JP9627581U JPS582048U JP S582048 U JPS582048 U JP S582048U JP 9627581 U JP9627581 U JP 9627581U JP 9627581 U JP9627581 U JP 9627581U JP S582048 U JPS582048 U JP S582048U
Authority
JP
Japan
Prior art keywords
instructions
input information
branch
test
order execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9627581U
Other languages
Japanese (ja)
Inventor
勝史 井上
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP9627581U priority Critical patent/JPS582048U/en
Publication of JPS582048U publication Critical patent/JPS582048U/en
Pending legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例による試験装置構成図、第２図
は情報入力例、第３図は第２図に関するフローチャート
を示す。 図において１は入力部、２は書込み制御回路、３は退避
メモリ、４はアドレスポイン゛り、５はオーダの異常終
了検出フラグ、６はオーダ実行後の状態情報メモリ、７
はオーダ発行回路、８は制御回路、９は読出し回路、１
０は入出力装置を示す。FIG. 1 is a configuration diagram of a test apparatus according to an embodiment of the present invention, FIG. 2 is an example of information input, and FIG. 3 is a flowchart related to FIG. 2. In the figure, 1 is an input section, 2 is a write control circuit, 3 is a save memory, 4 is an address point, 5 is an order abnormal end detection flag, 6 is a state information memory after order execution, and 7
is an order issuing circuit, 8 is a control circuit, 9 is a readout circuit, 1
0 indicates an input/output device.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のオークを組み合せて、ある命令を行う装置を試験
する試験装置において、オーダの発行、オーダの実行後
の異常終了によって分岐する命令、オーダ実行後の状態
情報の条件により分岐する命令および無条件分岐命令を
組み合せた複数のステップの入力情報を格納するメモリ
と、該入力情報のステップを管理するアドレスポインタ
と、前記命令を実行する制御回路と、前記入力情報を入
力する入力手段を有す不ことを特徴とする試験装置。In a test device that combines multiple orcs to test a device that executes a certain instruction, there are instructions that branch due to order issuance, abnormal termination after order execution, instructions that branch based on the condition of status information after order execution, and unconditional instructions. A component comprising a memory for storing input information of a plurality of steps combining branch instructions, an address pointer for managing steps of the input information, a control circuit for executing the instructions, and an input means for inputting the input information. A test device characterized by:
JP9627581U 1981-06-29 1981-06-29 test equipment Pending JPS582048U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9627581U JPS582048U (en) 1981-06-29 1981-06-29 test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9627581U JPS582048U (en) 1981-06-29 1981-06-29 test equipment

Publications (1)

Publication Number Publication Date
JPS582048U true JPS582048U (en) 1983-01-07

Family

ID=29891146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9627581U Pending JPS582048U (en) 1981-06-29 1981-06-29 test equipment

Country Status (1)

Country Link
JP (1) JPS582048U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51105738A (en) * 1975-03-14 1976-09-18 Fujitsu Ltd
JPS54123053A (en) * 1978-03-17 1979-09-25 Fujitsu Ltd Tester

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51105738A (en) * 1975-03-14 1976-09-18 Fujitsu Ltd
JPS54123053A (en) * 1978-03-17 1979-09-25 Fujitsu Ltd Tester

Similar Documents

Publication Publication Date Title
JPS582048U (en) test equipment
JPS60238948A (en) Device for measuring processing time of computer system
KR890008681A (en) Processor control unit
JPS59180300U (en) memory test equipment
JPS6134662A (en) Microcomputer application apparatus
JPS5839649U (en) test circuit
JPS5836446U (en) Branch control circuit test equipment
JPS6095654U (en) data transfer control device
JPS6284354A (en) Trace instruction controlling system
JPS5949249U (en) program test system equipment
JPH0272443A (en) Data processor
JPS5839646U (en) data processing equipment
JPS6376948U (en)
JPS6112144U (en) program test equipment
JPS5940942U (en) processing equipment
JPS58151659A (en) Measuring device of logical analysis of data processing device
JPS5881654U (en) arithmetic processing unit
JPS6087050U (en) data transfer control device
JPS59169651U (en) Debugging device
JPS5844642U (en) Debugging device
JPS60101500U (en) shipping equipment
JPS63170752A (en) Trace circuit
JPS6250854B2 (en)
JPS5949252U (en) address control device
JPS59100346U (en) Microprogram operation storage device