JPS5839649U - test circuit - Google Patents

test circuit

Info

Publication number
JPS5839649U
JPS5839649U JP13435281U JP13435281U JPS5839649U JP S5839649 U JPS5839649 U JP S5839649U JP 13435281 U JP13435281 U JP 13435281U JP 13435281 U JP13435281 U JP 13435281U JP S5839649 U JPS5839649 U JP S5839649U
Authority
JP
Japan
Prior art keywords
test
input function
scan
microprogram
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13435281U
Other languages
Japanese (ja)
Inventor
和彦 二宮
五十嵐 秀男
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP13435281U priority Critical patent/JPS5839649U/en
Publication of JPS5839649U publication Critical patent/JPS5839649U/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のテスト回路の構成図、第2図は本考案の
テスト回路の実施例のブロック図、第3図は第2図を構
成する各要素の論理値の説明図である。 201.202・・・選択回路、210,211・・・
記憶部、240・・・テスト・フィールド、241・・
・ディストネーションフィールド。
FIG. 1 is a block diagram of a conventional test circuit, FIG. 2 is a block diagram of an embodiment of the test circuit of the present invention, and FIG. 3 is an explanatory diagram of the logical values of each element constituting FIG. 201.202...Selection circuit, 210,211...
Storage section, 240...Test field, 241...
・Destination field.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロ・プログラムによって制御される演算処理装置
において、被テスト・デ、−夕ののマスク・パターンを
格納し、且つマイクロ・プログラムの書き込み命令及び
スキャン・インによる入力機能を有する第1の記憶部と
、目的とするテストの成立条件を示す期待値パターンを
格納し、且つマイクロ・プログラムの書き込み命令及び
スキャン・インによる入力機能を有する第2の記憶部と
、マイクロ拳プログラムのテスト・フィールド及びディ
ストネーション・フィールドによって、前記第1並びに
第2の記憶部をアドレスする手段と、前記第1の記憶部
の出力データで被テスト・データをマスクする機能を有
するゲート回路と、上記ゲート回路の出力と前記第2の
記憶部の出力とを比較して、テスチ結果を出力する比較
回路と、で構成され、前記第1並びに第2の記憶部に対
して、マイクロ・プログラムの書き込み命令あるいはス
キャン・インによる入力機能を用いて任意のパターンを
入力することによって、任意のテスト条件を設定できる
ように構成されてなることを特徴と   −したテスト
回路。
In an arithmetic processing unit controlled by a microprogram, a first storage unit stores a mask pattern of a device to be tested and has an input function by a microprogram write command and scan-in; , a second storage unit that stores an expected value pattern indicating the conditions for establishing the target test, and has an input function by a micro program write command and scan-in, and a test field and destination of the micro fist program. - means for addressing the first and second storage sections by fields; a gate circuit having a function of masking the data under test with the output data of the first storage section; a comparison circuit that compares the output of the second storage section and outputs a test result; A test circuit characterized in that it is configured such that arbitrary test conditions can be set by inputting an arbitrary pattern using an input function.
JP13435281U 1981-09-11 1981-09-11 test circuit Pending JPS5839649U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13435281U JPS5839649U (en) 1981-09-11 1981-09-11 test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13435281U JPS5839649U (en) 1981-09-11 1981-09-11 test circuit

Publications (1)

Publication Number Publication Date
JPS5839649U true JPS5839649U (en) 1983-03-15

Family

ID=29927780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13435281U Pending JPS5839649U (en) 1981-09-11 1981-09-11 test circuit

Country Status (1)

Country Link
JP (1) JPS5839649U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134755U (en) * 1985-02-09 1986-08-22
JPH0294751U (en) * 1989-01-11 1990-07-27
JPH0611642U (en) * 1991-12-05 1994-02-15 有限会社森井 Portable insulation box

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134755U (en) * 1985-02-09 1986-08-22
JPH0243312Y2 (en) * 1985-02-09 1990-11-19
JPH0294751U (en) * 1989-01-11 1990-07-27
JPH0611642U (en) * 1991-12-05 1994-02-15 有限会社森井 Portable insulation box

Similar Documents

Publication Publication Date Title
JPS5839649U (en) test circuit
JPS59180300U (en) memory test equipment
JPS59117974U (en) Measurement mode switching circuit
JPS59113774U (en) Automatic measurement device for semiconductor device characteristics
JPS5949249U (en) program test system equipment
JPS6125687U (en) Multi-point input detection circuit
JPH0474345U (en)
JPS5836402U (en) Sequencer
JPH06259495A (en) Logic simulation system
JPH02216543A (en) System for recognizing action of micro program
JPS5815243U (en) word processor
JPS5851354U (en) arithmetic device
JPS58149822U (en) flip-flop circuit
JPS5836446U (en) Branch control circuit test equipment
JPS6137538U (en) microprogram controller
JPS5956845U (en) counter circuit
JPS59100306U (en) Sequence control calculation device
JPS58182529U (en) Multiple input/output gate device using PROM
JPS5819345U (en) information processing equipment
JPS5991068U (en) highway test equipment
JPS6087047U (en) Control device
JPS5912193U (en) tuning device
JPS58179503U (en) Sequence control device counter circuit
JPS59182757U (en) Microcomputer malfunction analysis circuit
JPS6383825U (en)