JPS58179503U - Sequence control device counter circuit - Google Patents

Sequence control device counter circuit

Info

Publication number
JPS58179503U
JPS58179503U JP7502982U JP7502982U JPS58179503U JP S58179503 U JPS58179503 U JP S58179503U JP 7502982 U JP7502982 U JP 7502982U JP 7502982 U JP7502982 U JP 7502982U JP S58179503 U JPS58179503 U JP S58179503U
Authority
JP
Japan
Prior art keywords
circuit
control device
control
sequence control
processing program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7502982U
Other languages
Japanese (ja)
Inventor
康弘 高橋
小長谷　宏一
Original Assignee
株式会社日立製作所
日立エンジニアリング株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所, 日立エンジニアリング株式会社 filed Critical 株式会社日立製作所
Priority to JP7502982U priority Critical patent/JPS58179503U/en
Publication of JPS58179503U publication Critical patent/JPS58179503U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はカウンター回路分ロジックブロック図、第２図
は第１図の動作原理説明図である。 １、　３．５．７．９．　１０・・・ＡＮＤ回路、２゜
４、　６．　８・・・ＦＦ回路、１１・・・ＯＲ回路。FIG. 1 is a logic block diagram of a counter circuit, and FIG. 2 is a diagram illustrating the operating principle of FIG. 1. 1, 3.5.7.9. 10...AND circuit, 2°4, 6. 8...FF circuit, 11...OR circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入出力回路と、この入出力回路から制御対象の各状態を
取り込み、論理演算を行なって、出力口゛　路を介して
前記制御対象へ出力を供給する論理演算回路と、この論
理演算回路の実行する処理プログラムを記憶する記憶回
路と、前記全ての回路の総括制御を行なう制御回路とか
らなり、制御処理プログラムをくり返し演算処理するこ
とで、前記制御対象の制御を行なうシーケンス制御装置
において、前記制御処理プログラム中に置かれ、指定さ
れた入力のうち、ＯＮ状態の入力のカウントを行ない、
ＯＮまたはＯＦＦを出力することを特徴とするシーケン
ス制御装置カウンター回路。an input/output circuit, a logic operation circuit that takes in each state of the controlled object from this input/output circuit, performs a logical operation, and supplies an output to the control object via an output port; and an execution of this logic operation circuit. In the sequence control device, the sequence control device is composed of a memory circuit that stores a processing program to perform the control, and a control circuit that performs overall control of all the circuits, and controls the control target by repeatedly performing arithmetic processing on the control processing program. Placed in the processing program, counts the inputs that are in the ON state among the specified inputs,
A sequence control device counter circuit characterized by outputting ON or OFF.
JP7502982U 1982-05-24 1982-05-24 Sequence control device counter circuit Pending JPS58179503U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7502982U JPS58179503U (en) 1982-05-24 1982-05-24 Sequence control device counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7502982U JPS58179503U (en) 1982-05-24 1982-05-24 Sequence control device counter circuit

Publications (1)

Publication Number Publication Date
JPS58179503U true JPS58179503U (en) 1983-12-01

Family

ID=30084417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7502982U Pending JPS58179503U (en) 1982-05-24 1982-05-24 Sequence control device counter circuit

Country Status (1)

Country Link
JP (1) JPS58179503U (en)

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