JPS5876934U - signal processing device - Google Patents
signal processing deviceInfo
- Publication number
- JPS5876934U JPS5876934U JP17064181U JP17064181U JPS5876934U JP S5876934 U JPS5876934 U JP S5876934U JP 17064181 U JP17064181 U JP 17064181U JP 17064181 U JP17064181 U JP 17064181U JP S5876934 U JPS5876934 U JP S5876934U
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- circuit
- central processing
- switching means
- processing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示すものであって、第1図は
信号切換装置の回路図、第2図A〜第2図Cは回路動作
を説明するための波形図である。
なお図面に用いられる符号において、1・・・スイッチ
回路、2・・・第1回路、3・・・スイッチ手段、4・
・・第2回路、CPU・・・中央処理装置、FROMl
、。
FROM2・・・情報源。The drawings show one embodiment of the present invention, and FIG. 1 is a circuit diagram of a signal switching device, and FIGS. 2A to 2C are waveform diagrams for explaining the circuit operation. In addition, in the symbols used in the drawings, 1... switch circuit, 2... first circuit, 3... switch means, 4...
...Second circuit, CPU...Central processing unit, FROMl
,. FROM2... Information source.
Claims (1)
これを上記中央処理装置に対して接続するスイッチ回路
と、上記スイッチ回路の接続動作に応答して制御信号を
出力する第1回路と、電源投入時においてリセット状態
に初期設定され、上記第1回路の制御信号に応答してセ
ット状態に反転されるスイッチング手段と、電源投入時
における上記スイッチング手段の出力によりゲートを開
いて上記中央処理装置をリセット状態に制御し、上記ス
イッチ手段がセット状態の時の出力により上記ゲートを
閉じて上記中央処理装置をセット状態に制御する第2回
路とを具備したことを特徴とする信号切換装置。Select a central processing unit and one of multiple information sources,
a switch circuit that connects this to the central processing unit; a first circuit that outputs a control signal in response to a connection operation of the switch circuit; and a first circuit that is initially set to a reset state when the power is turned on; a switching means that is inverted to a set state in response to a control signal of the switching means, and an output of the switching means when the power is turned on to open a gate and control the central processing unit to a reset state, and when the switching means is in the set state; and a second circuit that closes the gate and controls the central processing unit to a set state by the output of the signal switching device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17064181U JPS5876934U (en) | 1981-11-16 | 1981-11-16 | signal processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17064181U JPS5876934U (en) | 1981-11-16 | 1981-11-16 | signal processing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5876934U true JPS5876934U (en) | 1983-05-24 |
Family
ID=29962594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17064181U Pending JPS5876934U (en) | 1981-11-16 | 1981-11-16 | signal processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5876934U (en) |
-
1981
- 1981-11-16 JP JP17064181U patent/JPS5876934U/en active Pending
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