JPS5953410U - Sequence control device - Google Patents

Sequence control device

Info

Publication number
JPS5953410U
JPS5953410U JP4266083U JP4266083U JPS5953410U JP S5953410 U JPS5953410 U JP S5953410U JP 4266083 U JP4266083 U JP 4266083U JP 4266083 U JP4266083 U JP 4266083U JP S5953410 U JPS5953410 U JP S5953410U
Authority
JP
Japan
Prior art keywords
input
output
address
output device
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4266083U
Other languages
Japanese (ja)
Inventor
増田 郁郎
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP4266083U priority Critical patent/JPS5953410U/en
Publication of JPS5953410U publication Critical patent/JPS5953410U/en
Pending legal-status Critical Current

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  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来方式によるシーケンス制御装置の一般的な
例を示すブロック図であり、第2図はその命令構成を示
す。第3図は本考案によ為シーケンス制御装置の一実施
例を示すブロック図であり、第4図はその命令構成を、
第5,6図はプログラム例をそれぞれ示す。 1・・・論理演算部、2・・・記憶装置、3・・・プロ
グラムカウンタ、4〜8・・・制御対象、9〜13・・
・入出力装置、14・・・退避用レジスタ、15・・・
マルチプレクサ、16・・・バイアス設定用レジスタ、
17・・・加算回路。
FIG. 1 is a block diagram showing a general example of a conventional sequence control device, and FIG. 2 shows its command structure. FIG. 3 is a block diagram showing an embodiment of the sequence control device according to the present invention, and FIG. 4 shows its command structure.
5 and 6 show example programs, respectively. DESCRIPTION OF SYMBOLS 1...Logic operation part, 2...Storage device, 3...Program counter, 4-8...Control object, 9-13...
・I/O device, 14... Save register, 15...
Multiplexer, 16...bias setting register,
17...Addition circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入出力番地で番地づけされる制御対象の各状態の入力お
よび制御対象への各状態の出力を行う入出力装置と、前
記入出力装置から制御対象の各状態を取り込み論理演算
を行って前記入出力装置に制御対象への出力を供給する
論理演算装置と、プログラム番地に番地づけされた前記
論理演算装置で処理する命令群および対応する入出力装
置の番地を記憶する記憶装置と、前記命令群に対応する
番地を指定するプログラムカウンタとを有するシーケン
ス制御装置において、前記論理演算装置の制御の下で前
記入出力番地のバイアス値を前記記憶装置中の命令に従
って記憶するバイアス値レジスタと、前記バイアス値レ
ジスタと命令に対応して指定されている入出力番地によ
り入出力装置を指定し前記バイアス値レジスタの出力と
命令に対応している入出力番地の和を出力する入出力番
地出力装置と、前記論理演算装置の制御の下に前記プロ
グラムカウンタの内容を一時的に退避し命令に応じてプ
ログラムカウンタの内容を変更させる退避レジスタとを
有することを特徴とするシーケンス制御装置。
An input/output device that inputs each state of the controlled object and outputs each state to the controlled object, which is addressed by an input/output address; and an input/output device that takes each state of the controlled object from the input/output device and performs a logical operation to a logical arithmetic unit that supplies an output to a controlled object to an output device; a storage device that stores a group of instructions to be processed by the logical arithmetic unit that are addressed to a program address and the address of a corresponding input/output device; and a storage device that stores the address of the corresponding input/output device; a program counter that specifies an address corresponding to a bias value register that stores a bias value of the input/output address according to an instruction in the storage device under the control of the logic operation device; an input/output address output device that specifies an input/output device by the value register and the input/output address specified corresponding to the instruction, and outputs the sum of the output of the bias value register and the input/output address corresponding to the instruction; A sequence control device comprising: a save register that temporarily saves the contents of the program counter under the control of the logical arithmetic unit and changes the contents of the program counter according to an instruction.
JP4266083U 1983-03-23 1983-03-23 Sequence control device Pending JPS5953410U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4266083U JPS5953410U (en) 1983-03-23 1983-03-23 Sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4266083U JPS5953410U (en) 1983-03-23 1983-03-23 Sequence control device

Publications (1)

Publication Number Publication Date
JPS5953410U true JPS5953410U (en) 1984-04-07

Family

ID=30173194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4266083U Pending JPS5953410U (en) 1983-03-23 1983-03-23 Sequence control device

Country Status (1)

Country Link
JP (1) JPS5953410U (en)

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