JPH082727Y2 - Programmable sequencer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a programmable sequencer that inputs signals, sequentially executes sequence programs, and outputs execution results, and particularly enables high-speed processing of sequence programs. Programmable sequencer.

[Conventional technology]

Conventionally, as this kind of programmable sequencer,
There is known a programmable sequencer in which an operation instruction code of a sequence program and data for designating an address of a memory for external input / output signals and an internal signal are stored in the same memory area.

FIG. 4 shows an example of the circuit configuration of a conventional programmable sequencer.

In FIG. 4, 1 is a sequence program memory 2
Is a microcomputer that executes a sequence program stored in a computer.
U) 11, a read only memory (ROM) 12 for storing a system program for operating the CPU 11, and a random access memory (RAM) 13 for storing variables used in the sequence program.

Reference numeral 3 is an internal signal memory for storing internal signals used as operation information in the sequence program, and 4 is an external input signal sent from an external device connected to the programmable sequencer or a result of operation processing by a microcomputer. An external input / output buffer that is temporarily stored for output to an external device. The operation of such a programmable sequencer will be described with reference to the flowchart of FIG.

In order to execute the arithmetic processing of the sequence step in the sequence program, first in step S1, the microcomputer 1 stores the address of the signal to be arithmetically processed stored in the internal signal memory 3 or the external input / output buffer 4 from the sequence program memory 2. Read the data.

Next, in step S2, the microcomputer 1
Reads the execution instruction code from the sequence program memory 2 and performs a predetermined operation based on the signal of the internal signal memory 3 or the external input / output buffer 4 in step S3. Finally, in step S4, the microcomputer 1 counts up the sequence steps and ends the one-step arithmetic processing.

[Problems to be solved by the invention]

However, in such a conventional programmable sequencer, since the address data of the signal to be arithmetically processed and the instruction code for the sequence arithmetic processing are stored in the same memory, when the microcomputer 1 executes the instruction of one step, Two kinds of data, signal address data and instruction code, must be input from the sequence program memory 2, and then an internal signal or an external signal of the memory address indicated by the address data must be input, and a total of three signal inputs are performed. Therefore, there is a problem that the calculation processing time is delayed.

Therefore, the purpose of the present invention is to solve such problems,
It is to provide a programmable sequencer capable of high-speed arithmetic processing of a sequence program.

[Means for solving problems]

In order to achieve such an object, the present invention provides a program storage means for storing a sequence program, an input / output means for storing an external signal, an internal signal storage means for storing an internal signal, the external signal and the internal signal. In a programmable controller having arithmetic processing means for executing the sequence program in response to a signal, the program storage means is stored in the instruction code storage means for storing the instruction code of the sequence program and the instruction code storage means. Sequence step control in which the storage address corresponding to the storage address of the instruction code is separated into address storage means for storing the address data of the external signal and the internal signal, respectively, and the addresses in the instruction code storage means and the address storage means are designated. Means, Less storage means, corresponding to the stored address data of the address indicated by the sequence step control means, characterized by being adapted to set the address of said input means and said internal signal storage means.

[Action]

According to the present invention, an instruction code for sequence operation processing and a storage address of data used in this instruction code are stored in different storage means by associating the storage addresses with each other, and in response to an instruction from the sequence step control means. Since the address of the above instruction code is set and the address storage means is set to store the storage address of the data used in the instruction code, the number of signal readings of the arithmetic processing means can be reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail and specifically with reference to the drawings.

 FIG. 1 shows an example of the configuration of the embodiment of the present invention.

In FIG. 1, the sequence program is separated into an instruction code for arithmetic processing and address data of a signal to be processed, and an instruction code storage means 50 and an address data storage means are provided.
51 and 51 are stored respectively.

The arithmetic processing means 53 for executing the sequence command gives a reading instruction signal to the sequence step control means 52.
When the sequence step control means 52 inputs this read instruction signal, the sequence step control means 52 sets the data storage address of the instruction storage means 50 for storing the sequence instruction code of the designated step.

Further, by simultaneously designating the data storage address of the address data storage means 51, the data storage address of the external signal input / output means 54 or the internal signal storage means 55 stored at the address designated by the address is set by the address storage means. To be done. Therefore, the arithmetic processing means 53
In this case, the reading of the instruction code from the instruction code storage means 50 and the reading from the external signal input / output means 54 or the internal signal storage means 55, that is, a total of two readings and inputs may be performed.

Further, if the arithmetic processing means 53 performs the arithmetic processing after outputting the reading instruction signal of the next step to the step control means 52, the step control means causes the instruction code storage means 50 before the arithmetic processing means 53 performs the arithmetic processing. , External signal input / output means
Since the address to be read by the arithmetic processing means 53 in the 54 or the internal signal storage means 55 is set in advance, the arithmetic processing means 53, upon completion of the arithmetic processing of one step, immediately outputs the instruction code and the internal signal of the next step or the external signal. It is possible to read the signal.

FIG. 2 shows an example of a concrete circuit configuration in the embodiment of the present invention.

In FIG. 2, 21 is a counter as the step control means 52, 24 is an external input / output buffer as the external signal input / output means 54, and 25 is an internal signal memory as the internal signal storage means 55.

In addition, internal signal memory 25 and external input / output buffer 24
The address input side of is connected to the output side of the sequence address memory 23 via the sequence address bus 26.

The output side of the counter 21 is connected to the address input side of the sequence instruction code memory 22 and the address memory 23 of the sequence program memory 2'via the step control address bus 27.

In such a configuration, the microcomputer 1 '
Outputs a load signal for setting the start step to the sequence step control counter 21 via the signal line 29.

Next, the counter 21 turns the sequence instruction code memory 22
When the instruction code read address is designated via the signal line 27, the instruction code memory 22 outputs a sequence instruction corresponding to the start step to the microcomputer 1'via the data bus 28.

Since the address instruction of the counter 21 is also sent to the sequence address memory 23 at the same time, it is processed from the sequence address memory 23 at the start step of the sequence program. For example, the input / output address data is externally input / output via the sequence address bus 26. It is output to the buffer 24. Therefore, the microcomputer 1 ′ can read the signal to be processed at the sequence start step almost simultaneously with the sequence command code from the external input / output buffer 24 via the data bus 28.

The microcomputer 1'ends the sequence calculation of the start step and outputs the calculation processing result to the external input / output buffer.
Then, the microcomputer 1'outputs the clock signal to the counter 21 and causes the counter 21 to output the instruction data for the next step. After that, the sequence instruction code and the signal to be processed are simultaneously selected by the microcomputer 1'as in the start step, so that the arithmetic processing time of the microcomputer 1'can be shortened.

FIG. 3 shows an example of the configuration of the sequence instruction code memory 22 and the sequence address memory 23.

In FIG. 3, the sequence program memory 2 '
Has a sequence instruction code memory 22 as an instruction code storage means 50 for storing an operation processing code in each step and a sequence address memory 23 as an address data storage means 51 for storing signal address data. The address memory 23 is provided with a storage area for storing the storage address of the processing signal (internal / external signal) used in the instruction code in each step. The address number of the storage area is made to coincide with the address number of the storage area for storing the instruction code of each step in the instruction code memory 22.

That is, when the instruction code of step 1 is stored at the address “0000” (decimal system) of the instruction code memory 22 and the instruction code of the nth step is stored at the address “000 (n−1)”, The storage address information of the processing signal used by the instruction code of 1 is set to the address “0000” (decimal system) of the address memory 23, and the storage address of the processing signal used by the instruction code of the nth step is set to “000 (n−1). ) ”
Will be stored in sequence. Further, by setting the addresses of the instruction code memory 22 and the address memory as described above, the counter 21 can perform only one type of address instruction.

[Effect of device]

As described above, according to the present invention, the microcomputer can simultaneously read the sequence command code and access the signal to be processed without addressing the processing signal by the microcomputer itself. The effect that high-speed sequence operation can be executed is obtained. In addition, since the program storage means itself has an address setting function, a dedicated address setting circuit is unnecessary and the device configuration is simplified. Also,
Since the instruction code storage means and the address storage means are separated, the instruction code and the address of the access destination can be expanded to the maximum storage data length of each storage means.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration in an embodiment of the present invention, FIG. 2 is a block diagram showing a circuit configuration in an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing a configuration of a memory area in the embodiment of the present invention. FIG. 4 is a block diagram showing an example of the configuration of a conventional programmable sequencer, and FIG. 5 is a flowchart showing an example of a control procedure in the conventional programmable sequencer. 1,1 ′ …… Microcomputer, 2,2 ′ …… Sequence program memory, 3,25 …… Internal signal memory, 4,34 ……
External I / O buffer, 11 …… CPU, 12 …… ROM, 13 …… RA
M, 21 …… Counter, 22 …… Sequence instruction code memory, 23 …… Sequence address memory, 26 …… Sequence address bus, 27 …… Step control address bus, 28
...... Data bus, 29,30 …… Signal line.

Claims (1)

[Scope of utility model registration request] 1. A program storage means for storing a sequence program, an input / output means for storing an external signal, an internal signal storage means for storing an internal signal, and the sequence program in response to the external signal and the internal signal. In a programmable controller having arithmetic processing means for executing, the program storage means corresponds to an instruction code storage means for storing an instruction code of the sequence program and a storage address of the instruction code stored in the instruction code storage means. The storage means comprises a sequence step control means for separating the address data of the external signal and the internal signal into address storage means for storing the address data of the external signal, and a sequence step control means for designating an address in the instruction code storage means and the address storage means, respectively. , The sequence Corresponding to the storage address data of the address indicated by the step control unit, programmable sequencer being characterized in that so as to set the address of said input means and said internal signal storage means.