JP3139310B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor for transferring data used for operation of a digital signal processor (DSP) or the like from an external device to an internal data memory by direct memory access (DMA). And its direct memory access control method.

[0002]

2. Description of the Related Art A DSP used in an image processing device, a sound source device, and the like is provided with a data RAM (random data storage) provided therein.
Access memory) temporarily stores coefficient data and signal data supplied from outside, and stores the internal multiplier and ALU
After the arithmetic processing of these data is executed by the (arithmetic logic unit), various processing such as filtering is executed by storing the arithmetic result in the data RAM and outputting it to the outside. In this type of DSP, since the capacity of a data RAM provided inside is limited, coefficient data and signal data to be provided for arithmetic processing are supplemented by DMA transfer from an external memory or the like during arithmetic processing, and arithmetic processing is performed. The processing results are also stored in an external memory, etc.
MA transfer is performed. 2. Description of the Related Art Conventionally, DMA transfer between a memory inside a DSP and an external device is performed by a host CPU provided outside the DSP controlling a DMA controller that controls the DMA transfer in accordance with a calculation execution state of the DSP. I have.

[0003]

However, control of the DMA controller by the host CPU, that is, D
When the DMA transfer between the SP and the external device is controlled, there is a problem that a time loss for the cooperation between the DMA transfer by the host CPU and the arithmetic processing of the DSP occurs in both the DSP and the host CPU. is there. For example, when the DSP finishes the operation of the existing data and needs the next data, the DSP interrupts the operation and interrupts the host CPU. In response to the interrupt, the host CPU requests the DMA controller to start DMA, and performs data transfer. After the data transfer is completed, the host CPU
To restart the operation. As described above, a loss time of the interruption occurs on the DSP side, and a load of the interrupt processing occurs on the host CPU side.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and a digital signal processing apparatus and a digital signal processing apparatus which can eliminate the occurrence of a time loss due to cooperation with a CPU and improve the data processing efficiency of the entire system. An object of the present invention is to provide a direct memory access control method.

[0005]

A digital signal processing apparatus according to the present invention is capable of transmitting and receiving data to and from an external bus.
Transfer the data for arithmetic processing to the first bus
A plurality of second buses and any of these buses
Multiple data sources that can be individually accessed for
Memory and the second bus of these data memories.
Data processing between multiple accessible data memories
Processing means for performing the calculation, and calculation for controlling the processing means
A program memory for storing a program including instructions,
Instructions are read out sequentially from this program memory and each part is
Command decoding means for controlling, via the external bus
Connected to the CPU and started by the CPU
Digital signal that performs predetermined digital signal processing
In the processing device, the program is stored in the program memory.
The program is written directly between the operation instructions.
DMA instruction for re-access execution
And the command decoding means decodes the DMA command.
And activates external DMA control means independently of the CPU
And a data memory connected to the first bus and an external device.
Initiates direct memory access to
With the next operation instruction,
Controlling a stage to store data memos connected to said first bus.
Parallel with execution of direct memory access to memory
Between a plurality of data memories connected to the second bus
The execution of the arithmetic processing in is controlled .

[0006]

[0007]

SUMMARY OF] According to the digital signal processing apparatus according to the present invention, within the program of the digital signal processing apparatus, operation instruction previously moistened with DMA commands with, during execution of the program, if the DMA instruction is decrypted Furthermore, since the external DMA control means is activated to execute the DMA transfer, the host CPU does not need to be involved in the DMA transfer at all. Therefore, an interrupt to the CPU is not required, and the load on the CPU is reduced. Further, since DMA can be started directly from the digital signal processing device, the interruption time in the digital signal processing device is also reduced.

Further, according to the digital signal processing device of the present invention, a plurality of data memories which can individually access any of the plurality of buses are provided, and data is read and written for arithmetic processing. The data memory to be DMA-transferred and the data memory to be DMA-transferred are made independent, and a program in which a DMA instruction is arranged between operation instructions is executed to access another data memory during execution of DMA for one data memory. As a result, the data processing efficiency can be further improved.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a system configuration of a game machine according to one embodiment of the present invention. This system is configured by connecting various functional elements to three buses 2, 3, and 4 arbitrated by a system control unit (hereinafter, referred to as SCU) 1. The bus 2 has a CPU 5 for controlling the entire system.
And a work RAM 6 for providing a work area for the CPU 5
And a boot ROM (read only memory) 7 which stores a processing program at the time of system startup. A game source such as a game ROM 9 is connected to the bus 3. An image processor 11 and a sound source processor 12 are connected to the bus 4.

The SCU 1 includes a bus controller 21 for executing switching control of the buses 2, 3, and 4, a DMA controller 22 for performing DMA transfer of data and programs between an internal memory and an external circuit, and an internal controller. A DSP 23 for executing a product-sum operation of the coefficient data and the signal input data stored in the memory is provided.

FIG. 2 is a block diagram showing a more detailed configuration of the DSP 23. The DSP 23 has four data RAMs numbered 0, 1, 2, and 3 in the drawing.
30, 31, 32, and 33 are provided. These data RAMs 30 to 33 have four independent buses 34, 3
5, 36 and 37 can access each independently. That is, of the four buses 34 to 37, the D0 bus 34 is connected to the bus controller 21 via the bidirectional buffer 38, and communicates with the external buses 2, 3, and 4 via the bus controller 21. Data can be exchanged. D1 bus 35, X bus 36, Y
The bus 37 is an arithmetic bus inside the DSP 23,
The D1 bus 35 is also connected to the DMA controller 22.

Address terminals of the data RAMs 30 to 33 are provided with an address counter (CT) 4 provided for each of the data RAMs 30 to 33 and commonly connected to the D1 bus 35.
0, 41, 42, and 43 and the D0 bus 34
One of the addresses from the address register (RA) 44 used for the external common memory access connected to the selectors 45, 46, 47, and 48 respectively.
Is selected and given. In addition, each data RAM 30-
33 stores any one of the data on the D0 bus 34 and the data on the D1 bus 35 selected by the selection circuits 50, 51, 52, and 53. From each of the data RAMs 30 to 33, data is read out to an arbitrary bus selected from the four buses 34 to 37 via the gate circuits 54, 55, 56, and 57.

The program RAM 60 stores the DSP 23
Is a memory for storing a program that defines the execution of the program.
The program transferred by the MA is stored. Program RA
The address of M60 is a program counter (PC) 61
Given by The PC value is stored in the TOP register 63 from the external CPU 5 via the D0 bus 34 and the selection circuit 68 during the initial setting, and is stored via the D1 bus 35 and the selection circuit 68 during the DMA transfer of the program. Prior to execution, TOP via the selection circuit 62
It is saved in the register 63.

The instruction code read from the program RAM 60 according to the PC value is fetched by the fetch circuit 64 and decoded by the instruction decoder 65. The instruction decoder 65 controls each unit of the DSP 23 based on the decoding result, and rewrites various flags 66 of E, V, C, and S. The instruction decoder 65 also performs setting of parameters for the DMA controller 22 and control of starting DMA. In this case, the parameters fetched by the fetch circuit 64 are transferred to the DMA controller 22 via the gate circuit 67 and the D1 bus 35. Also, PC
The value and various flags 66 are stored in the TO
It is supplied from the P register 63 and the D0 and D1 buses 34 and 35 and is rewritten.
9 and transferred via the D0 bus 34 to the outside.

The multiplier 71 is selected by a selection circuit 72,
The data on the D1 bus 35 or the X bus 36 stored in the RX register 73 and the Y stored in the RY register 74
The data on the bus 37 is multiplied. The result of the multiplication is that the upper bit is the PH register 75 and the lower bit is
6, and is stored in the PL register 77. The data on the D1 bus 35 and the X bus 36 are also selected by the selection circuit 76 and stored in the PL register 77.
The ALU 78 adds the data stored in the PH and PL registers 75 and 77 and the data stored in the ACH and ACL registers 79 and 80. As a result of the addition, the upper bits are stored in the ACH register 79 and the lower bits are stored in the selection circuit 8.
1 and is output to the D1 data via the shift register 82 and the gate circuit 83 while being stored in the ACL register 80. With this configuration, it is possible to execute arithmetic processing such as a product-sum operation.

Next, the operation of this system will be described. First, the CPU 5 transfers the execution program of the DSP 23 stored in the work RAM 6 to the program RAM 60 of the DSP 23. At this time, since the capacity of the program RAM 60 of the DSP 23 is limited, the program is transferred by an amount that the program RAM 60 can store. Next, the CPU 5 transfers the PC value for activating the program of the DSP 23 to the PC 61. Further, the execution flag EX is set to 1 to start the program.

When the program of the DSP 23 is started,
After that, the DSP 23 independently executes the following processing without depending on the control of the CPU 5. FIG. 3 shows the program RAM 60.
And FIG. 4 is a flowchart showing the contents of processing executed by the program.

First, immediately after startup, the data RAM
30 to 33 include the coefficient parameters, the signal data for calculation, etc.
Since no data required for the SP processing is stored at all, it is necessary to store these data in the data RAMs 30 to 33. For this reason, a DMAC parameter setting instruction is arranged at the start address “0” of the program, followed by a DMA instruction and a DMA end confirmation instruction. When decoding the DMAC parameter setting command, the command decoder 65 outputs the following DMAC parameter to the D1 bus 35 and outputs a register write signal to the DMA controller 22. The DMAC parameters include, for example, a transfer source address, a transfer destination address, and a transfer word number. For example, the start address of the coefficient data storage area of the work RAM 6 is set as the transfer source address, and the coefficient data number is set as the transfer word number in the DMA controller 22. Then, the start address of the data RAM 30 is set in the address counter 40 as the transfer destination address. Then, the instruction decoder 65 sets the DM
When the A instruction is decoded, the DMA
A start signal is output. Thus, the DMA controller 22 executes the DMA transfer of the coefficient data from the external work RAM 6 to the internal data RAM 30 (S
1).

When the DMA is started, the TO flag becomes "1".
The TO flag maintains "1" until the A end signal is output. In the subsequent DMA end confirmation command, the system waits until the TO flag becomes "0" (S2). By the same processing, the operation input data is DMA-transferred from the outside to the data RAM 31 (S3, S4).

Further, by the same processing, the data RAM 3
2, the operation input data is DMA-transferred from outside (S
5) In this state, since the coefficient data and the operation input data are already stored in the data RAMs 30 and 31, respectively, the operation processing between these data can be executed.
Therefore, as soon as the DMA transfer to the data RAM 32 is started, the coefficient data stored in the data RAM 30 and the operation input data stored in the data RAM 31 are subjected to a product-sum operation using the multiplier 71 and the ALU 78. A process of storing the calculation result in the data RAM 33 is executed (S6). In this case, as shown in FIG. 5A, the data RAM is used to prevent data collision on the bus.
DMA transfer to the data RAM 30 is performed via the D0 bus 34, and reading of coefficient data from the data RAM 30 is performed on the X bus 3
6. The operation input data is read from the data RAM 31 via the Y bus 37, respectively.
The transfer result of each data is made independent so that the calculation result is written through the D1 bus 35. Thus, the DMA transfer to the data RAM 32 and the arithmetic processing by the data RAMs 30, 31, 33 can be executed in parallel.

When a series of arithmetic processing is completed, the DMA
An end confirmation command is executed (S7). As shown in FIG. 3, at the time of confirming the end of the DMA T1, the DMA processing is completed (T
In most cases, the waiting time for the next instruction is substantially eliminated. Next, the operation result stored in the data RAM 33 is transmitted to the outside via the D0 bus 34.
MA transfer is performed (S8). This situation is shown in FIG.
When the DMA end is confirmed (S9), the data RAM 3
1 starts the DMA transfer of the operation input data to S1 (S1).
0), followed by the coefficient data and data R in the data RAM 30.
The arithmetic processing with the arithmetic input data of AM32 is executed, and the arithmetic result is stored in the data RAM 33 (S11). This state is shown in FIG. After completion of the arithmetic processing, if the end of the DMA is confirmed (S12), the arithmetic result stored in the data RAM 33 is DMA-transferred externally (S1).
3). When the DMA end is confirmed (S14),
Steps S5 to S14 are repeated.

For example, as shown in FIG. 6, when DMA transfer is performed from the data RAM 33 to the outside,
The arithmetic processing is performed on the coefficient data stored in the data RAM 30 and the operation input data stored in the data RAM 32, and the processing of storing the operation result in the data RAM 31 is performed in parallel. Then, the time T3 at which the DMA transfer of the data RAM 33 ends.
In response to this, a DMA end confirmation instruction is arranged, and new operation input data is externally stored in the data RAM 33 from D.
MA transfer may be performed. FIG. 7 shows the data flow at this time. If the DMA transfer time is sufficiently shorter than the operation processing time, two DMA transfers to the data RAM 33 shown in FIGS. 7B and 7C, respectively, and the operation processing are performed in parallel, so that the efficiency is further improved. Processing is possible. In this case, the next arithmetic processing is performed in the data RAM
30 and the data RAM 33, during which the data RA
The data of M31 will be replaced.

In the above processing, an instruction for confirming the end of the DMA is inserted into the program. In particular, when the DMA transfer and the arithmetic processing are performed simultaneously, if the time required for the DMA is known in advance, the start of the DMA is performed. By arranging the next DMA transfer instruction or operation instruction after the PC value expected to be pointed at the time when the time required for the DMA transfer has elapsed from the above, the DMA end confirmation instruction can be omitted.

By the way, in order to realize the above processing, the values of the address counters (CT) 40 to 43 for giving the addresses to the respective data RAMs 30 to 33 can be rewritten by an instruction inside the DSP 23. DM
It must be incrementable from both A controllers 22. If the values of CTs 40 to 43 can be controlled by both the DSP 23 and the DMA controller 22 in this manner, depending on the description of software, depending on the nature of the system in which DMA transfer and arithmetic processing are performed in parallel,
Overlap (overhead) may occur between the data RAM during the DMA transfer and the data RAM accessed by the operation instruction. Therefore, each of the CTs 40 to 43 for giving an address to each of the data RAMs 30 to 33 has an S indicating that the data RAM has been selected for the DMA transfer.
It is desirable to provide the EL0 to SEL3 flags and to add an overhead prevention circuit as shown in FIG. 8 to the circuit shown in FIG.

In this overhead prevention circuit, the DMA
A DATARAM selection signal obtained from the C parameter;
An AND output with the DMA start signal from the instruction decoder 65 is obtained by the gate circuits 90 to 93, and the gate circuits 90 to 93
The flip-flop circuits 94 to 97 are set by the "1" output of the CPU, and the flip-flop circuits 94 to 97 are reset by the DMA end signal output from the DMA controller 22. As a result, of the data RAMs 30 to 33, the DM
A flip-flop 9 corresponding to the data RAM in execution
"1" output is obtained from 4-97. Based on the flags of SEL0 to SEL3 output from the flip-flops 94 to 97, the gate circuits 100 to 103 cause the instruction decoder 65
When the access signal of each of the data RAMs 30 to 33 output from the gate is gated, "1" is output from the gate circuits 100 to 103 corresponding to the data RAM to which the access is instructed by the instruction decoder 65 during DMA execution. When this is detected by the gate circuit 104, a PC standby signal is output to stop the program counter 61 and wait for the execution of the program. Thereby, the data RAM during the execution of the DMA
No access to the data RAM is possible, including rewriting of the address counters 40 to 43 corresponding to the data RAM. According to this configuration, a program can be described without considering the overhead.

Next, DMA transfer of a program will be described. As described above, if the program RAM 60 incorporated in the DSP 23 has a capacity limitation, the DSP 23
All programs to be executed at once
Cannot be stored in M60. Therefore, DSP23
During the program RA, as shown in FIG.
A DMA transfer instruction of the program to M60 is described. FIG. 10 shows the processing when the DMA instruction of this program is executed.

When the DMA instruction of the program is executed,
First, the current PC value is saved in the TOP register 63 (S21). That is, since the next DMAC parameter setting instruction has been prefetched into the fetch circuit 64 at the time of execution of the DMA instruction, the PC value indicates the next address (N in FIG. 9) of the DMAC parameter setting instruction.
This N is stored in the TOP register 63. By the following DMAC parameter setting command, the transfer source address, the transfer destination address and the number of transfer commands are set in the DMA controller 22, and the transfer destination address is set in the program counter 61 (S22). Next, the set instruction number is externally transmitted to the program R via the D0 bus 34.
The data is DMA-transferred to the AM 60 (S23). For example, when the transfer destination address is set to the next address N of the DMAC parameter setting command as shown in FIG. 9, new commands A, B,... Are stored in order from the next address of the DMAC parameter setting command. Will be done. When the set number of DMA transfers are completed, the PC value saved in the TOP register 63 is set in the program counter 61 (S24). Thereafter, the execution of the program is restarted from the instruction A following the DMAC parameter setting instruction.

As described above, by transferring the own program by DMA using the program of the DSP 23 itself, regardless of the capacity of the program RAM 60, any long program can be continuously performed without increasing the load on the CPU 5 at all. Can be executed.

[0029]

As described above, according to the present invention,
A DMA instruction is included in a program inside the digital signal processing device together with an operation instruction, and when the DMA instruction is decoded during the execution of this program, an external D
Since the MA control means is activated to execute the DMA transfer, the host CPU does not need to be involved in the DMA transfer at all and the load on the CPU is reduced, and the DMA is started directly from the digital signal processing device. Therefore, there is an effect that the interruption time in the digital signal processing device is also reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of a game machine according to one embodiment of the present invention.

FIG. 2 is a detailed block diagram of a DSP in the system.

FIG. 3 is a diagram showing an example of a program stored in a program RAM in the system.

FIG. 4 is a flowchart showing the contents of processing executed by the program.

FIG. 5 is a diagram for explaining a data flow in the same processing.

FIG. 6 is a diagram showing another example of a program stored in a program RAM in the system.

FIG. 7 is a diagram for explaining a data flow in processing executed by the program.

FIG. 8 is a circuit diagram of an overhead prevention circuit in the same system.

FIG. 9 is a diagram showing an example of a program using a DMA transfer instruction of the program in the same system.

FIG. 10 is a flowchart showing processing executed by the program.

[Explanation of symbols]

1: System control unit, 2, 3, 4 ...
Bus 5, CPU, 6 Work RAM, 7 Boot RO
M, 9: Game ROM, 11: Image processor, 12 ...
Sound source processor, 21 bus controller, 22 DM
A controller, 23 digital signal processor, 30 to 33 data RAM, 34 D0 bus, 3
5 D1 bus, 36 X bus, 37 Y bus, 40-4
3 ... Address counter, 44 ... Address register, 60
... Program RAM, 61 ... Program counter, 64
Fetch circuit, 65 ... decoder, 71 ... multiplier, 78 ...
ALU

Continuation of the front page (56) References JP-A-3-2695932 (JP, A) JP-A-61-271555 (JP, A) JP-A-2-129724 (JP, A) JP-A-61-151776 (JP) , A) JP-A-2-59845 (JP, A) JP-A-63-131367 (JP, A) JP-A-8-115291 (JP, A) US Patent 5765025 (US, A) (58) (Int.Cl. ⁷ , DB name) G06F 9/30-9/42

Claims (1)

(57) [Claims] 1. A first bus capable of transmitting and receiving data to and from an external bus, a plurality of second buses for transferring data for arithmetic processing, and an arbitrary bus among these buses. A plurality of data memories individually accessible to each other, arithmetic processing means for arithmetically processing data among the plurality of data memories accessible to the second bus among the data memories, and controlling the arithmetic processing means wherein C and program memory for storing a program including a computation instruction, and an instruction decode means for controlling each unit sequentially reads out the instruction from the program memory, it is connected to the CPU via the external bus to
Activated by PU to perform predetermined digital signal processing
In the digital signal processing device to be executed, the program stored in the program memory is one in which a DMA instruction for executing direct memory access is arranged between the operation instructions. When you decode the instructions, before
Independently of the CPU, the external DMA control means is activated to start direct memory access between the data memory connected to the first bus and the external device, and to continue the above operation by the next operation instruction. The arithmetic processing means is controlled to execute arithmetic processing between a plurality of data memories connected to the second bus in parallel with execution of direct memory access to the data memory connected to the first bus. A digital signal processor for controlling execution.