JPS62190544A - Higher link unit for programmable controller - Google Patents

Abstract

PURPOSE:To quickly fetch the change of each data to simplify a communication program by transmitting prescribed data to the host side without waiting for a request command in case a higher link unit is set to the data link level. CONSTITUTION:In case a normal command is sent from a host computer 3, a higher link unit 2 accesses an input/output memory 15 of a PC body 1 and returns its contents to the computer 3. In case a data link start command is sent, the unit 2 is set to the data link level, and hereafter, channel data designated by a higher link instruction is returned to the computer 3 indepedently of the presence or the absence of commands from the computer each time when a higher link service is performed on the side of the PC body 1. At the time of a data link terminating command is sent, the level of the unit 2 is changed, and hereafter, the unit 2 waits for a command from the computer 3 to access the PC body 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to an upper link unit of programmable controllers 1-roller.

(Summary of the invention) In this invention, for this type of upper link unit,
In addition to establishing a data link level as one of the link levels, if the upper link unit is set to the data link level, the programmable controller Each time a HALT ready signal is given from the controller, data within a set range is read out from the controller and sent to the host computer.

(Prior art and its problems) Conventionally, in this type of upper link unit, upon receiving a data request command from the postcomputer side, it accesses the input/output memory of the programmable controller and processes the requested data. Input/output data, etc. are sent back to the host computer.

Therefore, in order to transmit the data in the input/output memory to the host computer side, it takes extra time to send a data request command from the boss 1 to the computer side to the upper link unit each time, and the input/output data etc. It depends on the timing of importing changes in data to the computer from the boss 1 or on the timing of polling from the host computer, which results in a delay in importing data changes, and from the perspective of the user of the host computer, communication There were problems such as the program becoming complicated.

(Object of the Invention) An object of the present invention is to provide an upper link unit of a programmable controller that is suitable for rapidly capturing input/output data changes of a programmable controller and that is capable of simplifying a communication program on the host computer side. Our goal is to provide the following.

(Structure and Effect of the Invention) In order to achieve the above object, the present invention includes a link level control means for setting or canceling the setting of a link level to a data link level according to a command received from a host computer, and a link level control means for setting or canceling the setting of a link level to a data link level. data link control means for reading data in a range set on the controller side and transmitting it to the host computer side each time a HALT ready signal is given from the programmable controller roller. It is characterized by comprising the following.

According to such a configuration, after sending a command for setting the data link level to the upper link unit in advance, the programmable controller side responds to the command when the service time for the upper link unit arrives. Since the HALT ready signal is then given to the upper link unit, the execution result is obtained every time the command is executed for one scan without the need to send any transmission request command from the host computer to the upper link unit. Input/output data can be immediately transmitted to the host computer side, and in this case, if an upper link instruction is defined in the user program as shown in the embodiment, only the data specified by the user instruction and the program It is possible to send data to the host computer only under the conditions specified in .

(Description of Embodiments) FIG. 1 is a block diagram showing the configuration of a programmable controller system to which an upper link unit according to the present invention is applied.

As shown in the figure, the PC main body 1 and the upper link unit 2 are connected via a system bus 4, and the upper link unit 2 and the host computer 3 are connected via a communication line 5.

As is well known, the PC body 1 includes a CPU 10, a system program memory 11. Input/output device 12. User memory 131. Work memory 14 and input/output memory 1
5 and also has a built-in CPU HALT control circuit 16.

The CPU 10 operates according to the system program stored in the system program memory 11, and performs input/output update processing and instruction execution processing as described later.

Upper link service processing, tool service processing, etc. are performed cyclically in order.

The input/output device 12 receives an output from an external input device (limit switch, etc.) or sends an output signal to an external output device (relay, etc.).

The user memory 13 stores user programs appropriately created by the user, and in this embodiment, the user programs are created in correspondence with a ladder diagram.

The work memory 14 is used to store various intermediate results of calculations performed by the CPU 10.

The input/output memory 15 is provided with various storage areas such as a memory area corresponding to the number of input/output points of the input/output device 12, an auxiliary relay area, a counter area, a timer area, and a keep relay area. Now, the data in the specific area of the input/output memory 15 is transferred to the upper link unit 2.
The data can be imported to the host computer 3 via the .

As is well known, the upper link unit 2 is C
PU20. It includes a system program memory 21, a work memory 221, and a communication LSI 23.

The CPU 20 is mainly composed of a microprocessor, and operates according to a system program stored in a system program memory 21.

The work memory 22 is used to store intermediate results of various calculations performed by the CPU 20.

The communication LSI 23 performs a receiving operation from the host computer 3 and a transmitting operation to the host computer 3.

Next, FIG. 2 is a flowchart showing the structure of the control program of the PC main body, FIG. 3 is a flowchart showing the structure of the control program of the upper link unit 2, and FIG. 4 is a flowchart showing the structure of the control program of the host computer 3. The operation of the apparatus of this embodiment will be systematically explained below according to flowchart 1. Note that the hatched portions in each figure are newly added portions related to the present invention.

First, the control program for the PC main body will be explained. In FIG. 2, when the program is started by power-on, etc., various registers, flags, etc. are initialized as initial processing (step 200), and then upper link service processing is performed (step 201).

In this upper link service processing, as is well known, an IALT ready signal is given to the CPU 20 of the upper link unit 2 via the CPU HALT control circuit 16, and a HALT command is returned from the upper link unit 2 side. With this, the CPU 10 enters the HALT state and transfers occupation of the system bus 4 to the CPU 20 of the upper link unit 2.

(After) From now on, the CPU of the upper link unit 2
20 uses the system bus 4 to perform various processing on the PC main body 1 side, and upon completion of the processing, the CPU HALT
A HALT release command is sent back to the CPLJIO of the PC body 1 via the υI@ circuit 16.

Then, the CPU 10 on the PC main body 1 side is released from the HALT state, thereby ending the upper link service processing.

Tool service processing is then performed (step 20).
2) If a program console (not shown) is connected to the PC main body 1, monitor processing is performed in response to signals from the keyboard of the device.

Various processing such as programming processing is performed (step 202>, and upon completion of the processing, the process shifts to input/output updating processing.

In the input/output update process, as is well known, each input state of the input/output device 12 is transferred to the input canister of the input/output memory 15, and the output data of the input/output memory 15 is transferred from the input/output device 12 to an external device. The data is sent to the device (step 203).

Next, until the RUN flag is set to it 1 t+ (No in step 204), all outputs of the input/output device 12 are kept off (step 205), and the operations in steps 201 to 203 are repeated.

In contrast, a programming console (not shown)
When the RUN flag is set to 111 $1 by a signal from 111 (Yes at step 204), a transition to an instruction execution operation is made.

In this instruction execution operation, first the value of the program counter is initialized to the start address of the user instruction, and then (
Step 206), while incrementing the value of the program counter by 1 (step 213), sequentially read out the instructions specified by the program counter from the user memory 13 (step 207), and decode the contents (step 208); Instruction execution processing is performed according to the decoding result (steps 210, 211, 212>).

Regarding the details of the instruction execution process, as is well known, it refers to the input/output data of the input/output memory 15, performs specified logical operations, etc., and rewrites the contents of the output data with the results of the operations. is customary.

Here, in this embodiment, as particularly shown in FIG. 6, a new command word "upper link command" is defined in the user command. The "upper link instruction" is treated as one application instruction of the ladder chart type program.

The user needs to load the data link establishment relay contact when using the "upper link command". This contact is allocated to a read-only special auxiliary relay area provided by the system and is located at the data link level.
This is a relay that turns ON when it is established. Therefore, unless this contact is turned on, the "upper link command" will not be executed.

Further, the operand of the "upper link command" specifies the first link channel and the last link channel. This area includes the normal input/output relay area, data memo 1, timer/counter current value area, link relay area, and holding relay area.

It shall be possible to set special auxiliary relay areas, etc.

Therefore, in the flowchart of FIG. 2, the upper link instruction is read out from the user program (step 21).
If the data link establishment relay contact is in the ON state, an upper link command processing request is issued (step 211).

That is, if the data link establishment relay contact is in the ON state, the first and last link channel information written following the second monitor HLNK is sent to a predetermined area of the work memory 14 as an upper link command processing request. be.

The set contents determine which range of data is transmitted to the host computer 3 when the PC main body 1 is accessed from the host link unit 2 side, as described later.
This serves as reference information that indicates where to forward the data to.

In this way, on the PC main body side, when an upper link instruction is read during an instruction execution operation, an upper link instruction processing request is set depending on the ON/OFF state of the data link establishment relay contact.

Next, referring to FIG. 3, the control program for the upper link unit 2 will be explained.

When the program starts by turning on the power, etc., it first initializes various flags and registers through initial processing (step 30), receives a command from the host combination Goto (step 31 is negative), and sets the data link level. It enters a state of waiting for setting (step 32 negative).

In this state, when a normal command, that is, a data request command to return specific data in the input/output memory to the host computer side, is given from the host computer 3 side (Yes at step 31), the upper link unit side then sends the data from the PC main body 1 side. It enters a state of waiting for the arrival of a HALT ready signal (step 33).

Here, as explained in FIG. 2, when the upper link service process is started (step 201), the PC main body 1
A 1-IALT ready signal is received from CPLJIO via the CPU HΔLTt5 control circuit 16.

When the HALT ready signal arrives at the upper link unit 2 side in this way, the HΔLT ready interrupt processing starting from step 3301 is immediately started.

In this interrupt processing, first, HALT is sent to the PC main body 1 side.
After issuing a command to set the CPU 10 of the PC body 1 to the HALT state (Step 3301), and confirming that it is not at the data link level (Step 3302 negative) and that there is a command to be processed (Step 3303 Portrait). , and on the condition that it is not a data link start command (step 3304 negative), normal command processing is executed (step 3307).

In this normal command processing, the input/output data specified by the normal command is read from the input/output memory 15 of the PC main body 1, and is transferred to the work memory 22 of the upper link unit 2.
Store in.

After that, give a HALT release command to the PC main body 1,
After releasing the HALT state of the CPU 10 of the PC main body 1 (step 3308), the HALT ready interrupt is ended.

Next, a response creation process is executed to transmit the input/output data stored in the work memory 22 to the host computer 3 via the communication LSI 23.Step 3
4) Thereafter, the system is again in a state of waiting for a command from the viewer (No in step 31) and waiting for setting to the data link level (No in step 32).

In this way, when a normal command is received from the host computer 3 side, the input/output data specified by the command is read from the input/output memory 15 of the PC body 1 and sent to the host computer via the communication LSI 23. An operation is performed to send the data back to the computer 3 side.

Next, when a data link start command is given from the host computer 3 side (the present invention will be explained in detail), first, as described above, a command from the computer is received (Yes at step 31), and the host computer 3 waits for the upper link service. (Step 33), the HALT ready interrupt is started after waiting for the arrival of the HALT ready signal.

After that, a HALT ready signal is sent to the PC, and P
After setting the CPU 10 of the C main body 1 to the HALT state (
Step 3301), the command is not at the data link level (step 3302 negative), a command exists (step 3303 affirmative), it is a data link start command (step 3304 affirmative), and the PC body 1 is in the RUN state (step 3305N). After checking the link level flag (step 3306), the link level flag is changed to the data link level (step 3306).

After that, after releasing the HALT state of the PC (step 3308), a 1-tALT ready interrupt is generated.
- is completed, and a response indicating that a series of reception processes necessary for starting the data link level has been completed is returned to the host computer 3 (step 34).

Thereafter, in the CPLJ 20 of the upper link unit 2, the setting to the data link level is confirmed based on the state of the link level flag (Yes at step 32), and from then on, the PC body 1 becomes in a state where the upper link service is provided (step 33). .

Then, each time the PC executes a round of user commands,
When the upper link service process starts (step 20
1) Each time, a HALT ready interrupt is generated on the upper link unit 2 side, and a HALT command is given to the PC main body 1 (step 3301').

In this state, it is confirmed that it is at the data link level based on the contents of the flag (step 33021), and then it is confirmed whether an upper link instruction processing request is set on the PC main body side (step 3309).

Here, as described above, in this embodiment, an upper link instruction, which is a new instruction word, is defined in the user instruction, and the start and end channels of the data to be transferred are set in the work memory 14 by its execution. is being done.

Therefore, if it is determined that there is an upper link instruction processing request based on the contents of the work memory 14 (step 330
9 affirmative), the upper link unit 2 side reads the data in the specified area from the input/output memory 15 of the PC main body 1, stores it in the work memory 22, and subsequently reads the upper link command set in the work memory 14. To clear the processing request, step 3311), press H on the PC.
After releasing the ALT (step 3308), the HALT
End ready interrupt.

Next, in the response creation process, the input/output data read from the input/output memory 15 of the PC body 1 is transferred to the communication LSI.
23, it is sent back to the host computer 3 side.

In this way, after a data link start command is given from the host computer 3 side and the upper link unit 2 is set to the data link level based on this, a transmission request command is especially given from the host computer 3. Naturally, each time the upper link service time arrives on the PC main unit 1 side, the contents of the input/output data specified by the upper link command are transferred to the host computer 3 side each time according to the execution result of the upper link command. It will be sent back.

Therefore, once a data link start command is sent from the host computer 3 side and the upper link unit 2 is set to the data link level, changes in each data in the input/output memory 15 of the PC main body 1 can be handled with high speed response. The communication program can be imported into the host computer 3 side with ease, and the communication program on the host 1-computer 3 side does not have to be particularly complicated.

Next, when a data link end command is given from the host i/computer 3 side, it is determined in the HALT ready interrupt processing that there is a data link end command (step 3312); The link level is canceled from the data link level and set to the command processing level (step 3313).

Thereafter, the upper link unit 2 will perform various processes specified by the commands on the PC body 1 in accordance with the normal commands given from the host computer 3.

Next, the control program of the host computer will be explained with reference to the flowchart of FIG. When the host computer receives a command to continue outputting PC data at normal speed through keyboard input, etc. (step 40).
1 (No), a normal command is sent from the host computer 3 to the upper link unit 2 (step 402).

Then, as mentioned above, the upper link unit 2 side receives the normal command and operates the input/output camera 7 from the PC main body 1.
The contents of the designated data are read out and sent back to the postcomputer 3.

When the response is received in this way (step 403 affirmative), the computer 3 side of the host 1 performs preprogrammed data processing based on the returned input/output data.

For example, it reads the count value of the counter in the input/output memory 15 of the PC main body 1, checks the processing status of the workpiece material flowing on the line, and gives a new processing command (
Step 404).

In response, if a command is given from the keyboard of the host computer 3 to send PC data one after another at high speed (step 401 is affirmative), a data link start command is sent from the host 1 to the computer 3 to the upper lean unit 2. is performed (step 405).

Then, as described above, the upper link unit 2 side sets the link level to the data link level in accordance with this data link start command, and then gives a response to the host computer 3 indicating that the setting to the data link level is completed.

Then, based on the response being received (step 4064), the host computer side confirms that the data link start has been accepted (step 4064).
07).

Thereafter, each time the PC main unit 1 executes a user command, a series of data specified by the high-order link command is sent back to the host computer 3 from the high-order link unit 2 (steps 408 negative, 409 (step 410).

In other words, on the host computer 3 side, the PC main body 1
The data in the input/output memory 15 can be taken in without a delay of one scan, and data processing can be performed based on this data.

Next, when a data link termination command is given from the keyboard of the host computer 3 (step 408 affirmative)
, a data link termination command is sent from the host computer 3 to the upper link unit 2 (step 411).

Then, as mentioned above, on the upper link unit 2 side,
After the level change process from the data link level to the command processing level is performed, a response to that effect is returned.

When this response is received on the host computer 3 side (step 412), acceptance of the end of the data link is confirmed (step 413 affirmative), and the series of operations described above is repeated.

As explained above using the flowcharts in FIGS. 2 to 4, when a normal command is sent from the host computer 3 side, the upper link unit 2 side accesses the input/output memory 15 of the PC body 1 as before, and The contents are sent back to the host computer 3 side.

On the other hand, when the data link 6 (l start command) is sent from the host computer 3 side, the upper link unit 2 side sets it to the data link level, and from then on, regardless of whether there is a command from the post computer 3, the P
Every time the upper link service is performed on the C main unit 1 side,
The data of the channel specified by the upper link command is sent back to the host computer 3 side.

In addition, when a data link end command is sent from the host combination 1-3, the level is changed to the command processing level on the upper link unit 2 side, and from then on, it waits for a command from the host computer 3 as before, and then
This means that the C main body 1 will be accessed.

The above operations are collectively shown in the time chart of FIG.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a programmable controller system to which the upper link unit according to the present invention is applied, Fig. 2 is a flowchart showing the control program of the PC main body, and Fig. 3 is a flowchart showing the control program for the upper link unit 1. Flowchart showing the program, FIG. 4 is a flowchart showing the control program of host 1 to computer,
The figure is a time chart showing the mutual operations of the PC main unit, upper link unit, host 1 to computer in relation to each other.
The figure shows the upper link instruction newly defined in this invention.
- It is a ladder diagram showing the configuration. 1...Programmable controller main body 2...Upper link unit 3...Host computer

Claims (1)

[Claims] (1) A link level control means for setting or canceling the setting of the link level to the data link level according to a command received from the host computer, and a HALT ready signal from the programmable controller on the condition that the link level is set to the data link level. An upper link unit of a programmable controller, comprising: data link control means for reading data in a range set on the controller side and transmitting it to the host computer side each time the data is given.