JPS5939766B2 - multiplexer channel equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel device that controls data transfer between an input/output device and a memory in an information processing system.
In particular, the present invention relates to a multiplexer channel device that switches an input/output device that performs data transfer every time an interrupt from the input/output device or a channel activation command occurs.

Conventionally, multiplexer channels used in information processing systems have been implemented by being incorporated into a microprogram (μP) within a CPU (central processing unit) 11 shown in FIG.

FIG. 2 shows the processing sequence of the microprogram (μP). Phase 0 (PH0) in the diagram
fetches and decodes instructions. As a result of instruction decoding, if the instruction type requires address calculation or operand fetch, it passes through Phase 1 (PHI) and then passes through Phase 2 (PHI).
2) starts executing the command. For instruction types that do not require address calculation or operand fetch, PH0 to PH
Enter 2. When exiting phase 2, if there is an interrupt factor, the process enters phase 3 (PH3), where various interrupts are determined and processed. If there is no interrupt factor, the process moves to PH0. FIG. 3 shows interrupt processing from the input/output bus 12 (operation as a multiplexer channel) in phase 3 (PH3). After checking the device number of the input/output device 13 that is causing the interrupt (ST-A), the channel control block in the memory 14 is fetched and decoded (ST-B). The channel control block (hereinafter referred to as CCB) describes the contents of input/output operations, and its format is shown in FIG. In the figure, numeral 41 is a channel control word (CCW), which is a word that specifies the type of operation (read, write, etc.), chain, etc. 42 is a transfer start address (start address) of the memory to which data is to be transferred.

The number of transfer bytes in 43 specifies the data transfer area, the command specifies the command data to be sent to the input/output device 13, and the terminal character terminates the data transfer if it matches the data specified in this column. This is a specification to allow

44 is a column in which the channel (CH), input/output device address (DEV), channel and device status are stored when the CCB operation is completed, and the chain address 45 is a column in which the channel (CH), input/output device address (DEV), and channel and equipment status are stored when the CCB operation is completed. If there is a designation (specified in CCW4l), this field is used to designate the storage start address of the new CCB.

Now, in Fig. 3, when the CCB decoding (ST-B) is completed, data transfer is performed (ST-C), and it is determined whether or not the CCB operation is completed (ST-D), that is, the data specified by the CCB is It is determined whether the transfer of the area has been completed or whether an abnormality in the terminal character or input device 13 has been detected, and if it has been completed, the process moves to termination processing (ST-E) which notifies the program of the end of the operation.

If the above CCB operation is not completed, phase 0 (PH
O) and processes the next instruction. Figure 5 shows the CPU
11 is a timing chart of the phase transition of ll and the operation of the input device.

When the operation of I/O-1 that is performing the output operation is completed, interrupt ATN-0 is input to CPUll. CPUll
After executing instruction 13, enters PH3 and performs the interrupt processing shown in FIG. 11-0 indicates data transfer ST-C in FIG.

When the data transfer with CPUI is performed, the output operation of I/O-1 starts, and when it is finished, interrupt ANT-2 is generated.
enters. Thereafter, similar operations are performed for the number of transfer bytes specified by the CCB. Input operation I/0-2 generates an interrupt A when the operator presses the key and is ready to transfer data.
Multiply TN-1. After executing instruction 14, CPUll performs interrupt processing and performs data transfer 11-1. Input/output device 1 connected to input/output bus 12 in this way
A multiplexer channel is implemented that operates three at the same time. However, in the case of this method, Figures 2 and 5
As is clear from the figure, interrupt processing cannot be performed while the CPU 11 is executing an instruction.

Also, instructions cannot be executed during interrupt processing. That is, execution of an instruction may be delayed due to interrupt processing. Another drawback is that interrupts from the input/output device 13 cannot be accepted until the execution of an instruction is completed. The throughput of the system is improved by multiplexing the execution of instructions and the operation of the input/output device 13, but recently, the instruction execution time has become longer due to high-performance instructions, and the speed of the input/output device has become faster. As a result, it has become impossible to ignore the fact that the execution of instructions is forced to wait for interrupt processing, or that interrupt processing is made to wait because it is a high-performance instruction. The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a multiplexer channel in which there is no delay in interrupt processing due to instruction execution by the CPU, and further, there is no delay in instruction execution due to interrupt processing.

An embodiment of the present invention will be described below with reference to the drawings. 6th
The figure is a block diagram showing the system configuration.
1 is the CPU, 112 is the input/output bus (1/O-BUS)
, 113, 113... are input/output devices. 114 is a main memory, and 115 is a memory control device.

116 is a multiplexer channel targeted by the present invention;
117 is high-speed DMA (DirectMemOryAcc
ess) bus.

FIG. 7 shows the configuration of the multiplexer channel 116. In the figure, 201 is a high-speed bus driver/receiver circuit through which data on the high-speed DMA bus 117 passes, and 202 is a high-speed bus control circuit. 203 is a termination register that notifies CPUll of the end of CCB operation.

A read data register 204 holds read data from the memory.

A write data register 205 holds data written to the memo January 14.

A memory address register 206 holds a memory address for data transfer.

207 is C that holds the CCB start address notified to the channel by the channel start command from CPUll.
This is the CB address register.

208 is a device number register that holds the channel number and equipment number notified to the channel by the channel activation command from the CPUll.

209 is an internal bus A (A-BUS), and each register, R
This is a bus that carries AM and other data.

A read data buffer register 210 holds data to be sent to the input/output bus 112, and is also used as a register to hold data when the microcomputer 221 reads data from each register, RAM, etc.

A write data buffer register 211 holds data from the input/output bus 112, and is also used as a register to hold data from the microcomputer 220.

212 is a counter that holds the number of transferred bytes, and is decremented every time data is transferred with the input/output device 113.

213 is a RAM (random access memory), and C
CB, input/output data, etc. are stored.

A CCW register 214 holds the CCW stored in the RAM 2l3.

A decode ROM 215 decodes the CCW and informs the microprogram counter 217 of the execution start address of the microprogram.

216 is a ROM address selector, which is a gate that selects a branch destination for the microprogram counter 217.

A microprogram counter 217 holds the address of the next microprogram to be executed.

This counter 217 is set every time the microprogram is executed.
It is incremented by 1'' and holds data from the ROM address selector 216 in the case of a microinstruction that involves a branch. 218, ROM1219 in which a microprogram is stored, a ROM data register that holds read data from ROM218, 220, a microcomputer, 221, an input/output bus control circuit, 222, a control circuit for internal bus A2O9, 223, a test (TES)
T) Condition determination circuit.

224 is an internal bus B (B-BUS) through which input/output data with the microcomputer 220, input/output data of the input/output bus 112, etc. are passed.

225 is an input/output bus driver/receiver circuit for exchanging data with the input/output bus 112;

226 is a register that holds the device number that caused the interrupt;
227 is an SIO stack that holds the device number activated by the channel activation command, and 228 is a stack register that holds read data of the SIO stack 227.

The outputs of the registers 226 and 228 become address information of the RAM 2l3. Reference numeral 229 is an address register for holding a device number and sending it to the input/output bus 112.

The effect will be explained here.

When the CPU1ll starts the multiplexer channel 116, after writing the CCB of FIG. 4 on the memory 114,
The start I/O command (SIO) shown in FIG. 8 is executed. In Figure 8, 81 is the SIO instruction format and is 0P.
is an instruction code, R1 is a general register designation, and N is a subcode that designates a channel operation. 82 is the contents of the R1 register, where the channel number and machine number are specified.

83 is the contents of the R1+1 register, which specifies the termination key number and CCB address.

When CPUll executes the start I/O command, R1
(82), the contents of R1+1 (83) are sent to the multiplexer channel 116. The subsequent channel operation is
This will be explained with reference to the figures.

R1 (82), R1+1 (8
The content of 3) is the high-speed bus driver/receiver circuit 201.
The data is held in the device number register 208 and CCB address register 207 through the CCB address register 207. When the contents of Rl and Rl+1 are held in the registers 208 and 207, a request is transmitted from the high-speed bus control circuit 202 to the internal bus control circuit 222. When the internal bus control circuit 222 permits bus use, the data in the CCB address register 207 is held in the RAM 2l3, and the data in the device number register 208 is held in the SIO stack 227. This R.A.
When the above data is stored in the M213 and SO stack 227, an SIO acceptance signal is transmitted from the internal bus control circuit 222 to the TEST condition determination circuit 223. Then TE
The ST condition determination circuit 223 includes a selector 216 and a counter 2.
Test & SIO reception from ROM2l8 via 17
Read and execute the branch microprogram. Then, the microprogram read from the ROM 2l8 starts processing the SIO command. The SIO command processing will be explained below.

The microinstructions of the microprogram that processes the SIO instructions from the ROM 2l8 are sequentially read out, and first the SIO instructions are sent to the internal bus control circuit 222 via the ROM data register 219.
When an IO stack retrieval command is issued, internal bus control circuit 222 transfers the device number from SIO stack 227 to stack register 228. During this operation, the internal bus control circuit 222 operates to select the stack register 228 as the subsequent address of the RAM 2l3. Then R
A command to take out the CCB address from the RAM 2l3 and set it in the memory address register 206 is also output from the OM 2l8 to the internal bus control circuit 222 and executed.

Thereafter, a memory read command is issued from the ROM 2l8 to the high-speed bus control circuit 202. When a memory read command is issued, the high-speed bus control circuit 202 issues a bus use request to the memory control device 115, and when use of the bus 117 is permitted, the data in the memory address register 206 is sent to the memory control device 115. When the memory control device 115 operates to finish reading the memory from the main memory 14 and sends the read data to the channel 116, the data is held in the read data register 204. Then, a store command is output from the ROM 2l8 to the internal bus control circuit 222, and the data in the read data register 204 is stored in the RAM 2l3. As a result, the CCB in the main memo I month 14 is taken into the RAM 2l3 in the channel 116. Then, when the above-described operation is repeated and the CCB has been taken out, the internal bus control circuit 222 takes out the CCB into the CCW register 214 stored in the RAM 2l3 according to a microinstruction from the ROM 2l8. The output of CCW register 214 is decoded ROM2
It is used as the address signal for decode ROM2l5.
5, the CCW is decoded and the address of the next microprogram to be executed is sent to the ROM address selector 21.
6 to the microprogram counter 217. Therefore, the microprogram branches and the microinstruction of the microprogram that processes the CCB is transferred to ROM2.
The data are read out sequentially from l8. Write below with CCW (WRI
The operation when there is a TE) mode command is described. First, the microprogram issues a command to the input/output bus control circuit 221 to send the device number held in the address register 229 to the input/output bus in order to connect the input/output device 113 and the channel. After sending the device number to the input/output bus 112, the input/output bus control circuit 221 sends CADRLO9-1 of FIG. 9 to the input/output bus 112, which indicates that the bus information is the device number. When the input/output device 113 connected to the input/output bus 112 matches the data on the input/output bus 112 with the number unique to the device itself, the input/output bus interface circuit of the input/output device 113 shown in FIG. address flip-flop 301 is set. CSY from I/O (input/output device) with matching device number
When NLO9-2 returns, the input/output bus control circuit 22
2 stops sending the device address and CADRLO9-1. When CADRLO 9-1 in Figure 9 and 303 in Figure 10 change from active state to inactive state, CSYNLO9
-2 becomes inactive. Figure 9 shows channel 1/0
Figure 10 shows the operation of the input/output device 1.
This is an example of No. 13 input/output bus interface circuit. During transfer from a channel to an I/O, after the input/output bus control circuit 221 sends data to the input/output bus 112, a control signal indicating the meaning of the data is activated.
CADVLO9-4 means data to be output to I/O, and CCMDLO9-7 means command data. During channel I/O transfer, first a control signal is issued, the I/O outputs the requested data, and when CSYNLO 9-2 is returned, the control signal is made inactive. CSRQLO9-3 is a status data request signal, CDRQLO9-5 is an input data request signal, and CACKLO9-6 is an interrupt device number sending request signal. The CACKLO lines 304 in FIG. 10 are daisy-chained, with CTAKLO3O6 becoming the next I/O CACKLO3O4, 9-6. Therefore, interrupt flip-flop 307 is set to 1.
When CRAKLO3O4 comes to /O, the steering flip-flop 308 is set and CTAKLO3O
6 is not rolled. This determines the priority when interrupts occur at the same time. Furthermore, since subsequent data transfer is performed only with the I/O set by the address flip-flop 301 in FIG. 301. When the connection between channel 1/O is completed, the microprogram of channel 116 executes R.
The start address 42 stored in AM2l3 is set in the memory address register 206. Next, the number of transferred bytes 43 is set in the counter 212. After that, R.A.
After setting the data read into M2l3 into the read data buffer register 210, the status request signal CSRQLO9-3 is sent to the input/output bus 112 and the status data is taken in. The status is checked, and if there is no abnormality, the data in the read data buffer 210 is sent to the input/output bus 112. When the input/output device 113 receives the data (CSYNLO9-2 is returned), it subtracts "1" from the counter 212 and stores the data in the memory address register 206.
is incremented by "1" and stored in RAM2l3 again. Normally, the high-speed DMA bus 117 is configured with n times the data width of the input/output bus 112, so reading from the memory 114 is performed every time the number of transfer bytes 43 is an integer multiple of n.
Stored in M2l3. When the input/output device 113 completes its output operation, it issues an interrupt (CATNLO3O5) to the channel.

When an interrupt is accepted, CACKLO9-6, 304 is sent from the input/output bus control circuit 221, and the interrupt device number is set in the interrupt device number register 226. When the input/output bus control circuit 221 outputs CAKLO96, 3O4, the interrupt device number register 226 is selected as the subsequent address of the RAM 2l3. As with the SIO instruction, RAM2
The CCW of l3 is read to the CCW register 214, and thereafter data transfer is performed in the same sequence. Note that data is set to the address register 229 by using CCW in RAM.
This is done when taking out from 2l3. From now on, the human output device 11
A similar operation is performed every time there is an interrupt from 3, and when the contents of the counter 212 reach "O", the operation completion state, that is, the memory address 42 at the end of the transfer, the number of transferred bytes 43, the channel status, The device status 44 and the like are stored in the memory 114. As described in detail above, by using the multiplexer channel of the present invention in an information processing system, interrupts from input/output devices can be
Since the execution of instructions by the CPU is not made to wait for execution of instructions, and the execution of instructions by the CPU is not made to wait for interrupt processing, the processing performance and processing speed of the CPU can be significantly improved, thereby reducing system throughput. You can improve.

Furthermore, since it has a storage device for storing channel control programs, the frequency of access to the main memory can be reduced, thereby making it possible to use the main memory efficiently.

[Brief Description of the Drawings] Fig. 1 is a block diagram for explaining a conventional multiplexer channel, Fig. 2 is a diagram showing a processing sequence of a microprogram in the configuration of Fig. 1, and Fig. 3 is a block diagram for explaining a conventional multiplexer channel. Figure 4 showing the processing flow of phase 3 shown in Figure 4.
5 is a diagram showing a channel control block, FIG. 5 is a timing chart showing conventional CPU phase transitions and operation of input/output devices, FIG. 6 is a system block diagram showing an embodiment of the present invention, and FIG. 7 is a diagram showing a channel control block. is a block diagram showing the configuration of the multiplexer channel device in the above embodiment, FIG. 8 is a format diagram of the start 1/O command in the above embodiment, and FIG. 9 is an example of the operating state between channels and 1/O in the above embodiment. FIG. 10 is a circuit block diagram showing an example of the input/output interface circuit of the input/output device in the above embodiment. 111... CPU, 112... Input/output bus, 113... Input/output device, 114...
...Main memory, 115...Memory control device,
116...Multiplexer channel, 117.
...DMA bus, 201 ... High speed bus driver receiver circuit, 202 ... High speed bus control circuit, 203 ... Termination register,
204... Read data register, 205...
...Write data register, 206...Memory address register, 207...CCB address register, 208...Device number register, 209, 224... Internal bus, 210
... Read data buffer register, 211.
...Write data buffer register, 212...
...Counter, 213...RAM, 214
...{℃W register, 215...Decode ROM, 216...ROM address selector, 217...゜Micro program counter, 2
18...ROM, 219...ROM data register, 220...Microcomputer, 221...I/O bus control circuit, 222...
...Internal bus A control circuit, 223...T
EST condition determination circuit, 225... Input/output bus driver receiver circuit, 226... Interrupt device number register, 227... SIO stack, 22
8...Stack register, 229...
Address register.

Claims (1)

[Claims] 1. Means for holding the storage address of the channel control block connected to the direct memory access bus and notified by the channel activation command from the host device and the equipment number of the input/output device, and microprogram control for controlling the inside of the channel by the microprogram. a means for reading a channel control block from the main memory based on a storage address of the channel control block by a microprogram that executes the channel activation instruction from the control section; A storage section stores the block at an address specified by the device number, and in response to an interrupt request from the input/output device, reads a corresponding channel control block from the storage section using the input/output number of the input/output device. A multiplexer channel device comprising: means.