JP2504535B2 - Bus unit configuration method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A method of configuring a bus unit for controlling memory access in a computer, including a memory mainly for program access and a memory mainly for data access, so that both data and program can be accessed. Of the bus unit and the execution unit that are operated independently for the purpose of realizing the same high-speed performance as the dual bus, the bus unit is the auxiliary program counter and the auxiliary program counter. An incrementer that increments the output of the instruction register, an instruction register in which an instruction code is input through an instruction queue, and a data buffer in which data is stored. Is transferred on the resource bus In a method of configuring a bus unit that alternately executes a RAM access and a data access, a memory mainly for program access and an address / data shared bus are provided in the bus unit, and the address bus in the bus unit is A first connection line is connected to the resource bus and a second connection line is connected to the address / data sharing bus, and an address from the execution unit and a subsequent auxiliary program counter from the execution unit are connected. One of the addresses indicates a memory whose main purpose is the program access,
When the other indicates a memory whose main purpose is data access, the address / data shared bus and the resource bus in the bus unit are separately used to overlap program access and data access. Configure to run.

[Industrial applications]

The present invention relates to a bus unit configuring method, and more particularly to a bus unit configuring method for controlling memory access in a computer.

With the recent demand for high-speed computers, high-speed bus access is desired. Therefore, a method of configuring a bus unit in which a program bus and a data bus are separated has been proposed. However, in this method, the accessible area is often safely separated, so that it can be restricted when it is used. Therefore, it is necessary to eliminate this restriction.

[Conventional technology]

FIG. 5 shows a block diagram of an example of a conventional bus unit configuration method. In the figure, 1 is a bus unit that mainly controls the bus, and 2 is an execution unit that has a central processing unit (CPU) and the like, and mainly executes instructions.

3 is a resource bus, which is routed in the bus unit 1. Reference numeral 4 is an auxiliary program counter for program fetch, and 5 is an incrementer for the auxiliary program counter 4. Reference numerals 6 and 7 respectively denote an address bus and a data bus for transferring addresses and data to the CPU in the execution unit 2, and the address bus 6 is joined to the resource bus 3 via a joint portion 8. As a result, the resource bus 3
The address can be switched between the address from the address bus 4 and the address from the auxiliary program counter 4.

Reference numeral 9 is an instruction queue for fetching an instruction, and 10 is an instruction register for decoding the instruction code from the instruction queue. 11 is a data buffer for storing the data on the resource bus 3, 12 is an I / O interface, 13 is a memory, and 14 is a resource group.

In the bus unit 1 having such a structure, at the time of program access, the address fetched from the auxiliary program counter 4 is transferred via the resource bus 3 to the I / O interface 1
2, select one of the memory 13 and the resource group 14,
And the instruction is fetched from the specified address. This instruction is input to the instruction register 10 after being taken in the instruction queue 9. The output address of the auxiliary program counter 4 is incremented by 1 by the incrementer 5.

On the other hand, at the time of data access, the address sent from the address bus 6 of the execution unit 2 is placed on the resource bus 3 through the joint portion 8, and the I / O interface 12, the memory 13 designated by the address, or the designated address from the resource group is designated. Read the data.

After this data is temporarily stored in the data buffer 11,
It is transferred to the data bus 7.

In such a configuration, since there is one resource bus 3,
As shown in FIG. 6, data access and program access are performed alternately. In FIG. 6, A represents an address, and D represents a data or instruction transfer period (see FIG. 3,
The same applies to FIG. 8).

Further, as a conventional method of configuring a bus unit of a computer, there is a configuration as shown in FIG. 5, those parts that are the same as those corresponding parts in FIG. 5 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 7, 16 is a bus unit, 17
Is an execution unit, 18 is a resource bus used exclusively for data access, and program access is not performed.

Further, 19 is an address bus in the execution unit 17, 20 is a data bus in the execution unit 17, and 21 is a program fetch dedicated bus, which does not access data. Reference numeral 22 is a junction between the resource bus 18 and the address bus 19.

Further, 23 is an I / O interface dedicated to the program area, 24 is a read only memory (ROM) dedicated to the program area, 25 is an I / O interface dedicated to the data area, and 26 is
Is a resource group dedicated to the data area.

According to the bus unit 16 having such a configuration, the address from the execution unit 17 is transferred to the address bus 19 during data access.
Is transferred to the resource bus 18 via the junction 22 and I /
The O interface 25 or the resource group 26 is selected and data is taken out from the specified address. This data is temporarily stored in the data buffer 11 and then transferred to the data bus 20.

On the other hand, during program access, the address from the auxiliary program counter 4 is the program fetch dedicated bus 21.
To the I / O interface 23 or ROM 24
Is selected, and the instruction is read from the designated address. The read instruction is input to the instruction queue 9.

According to the conventional bus unit 16, the boundary between the program area and the data area is provided, and the resource bus 18 and the bus 21 are provided as shown in the time chart of FIG. Can be done in parallel at the same time.

[Problems to be Solved by the Invention]

However, in the conventional bus unit configuration method shown in FIG. 5, there is no boundary between the program area and the data area, and each of the I / O interface 12, the memory 13 and the resource group 14 has no program or data. However, since one resource bus 3 is shared, data access and program access must be performed alternately, and there is a drawback that the speed is slow.

On the other hand, according to another conventional bus unit configuration method shown in FIG. 7, since the boundary between the program area and the data area is provided, the program access and the data access can be performed in parallel, which is high speed. While it has features,
Since the resource bus 18 is not connected to the I / O interface 23 and the ROM 24, its main purpose is program access.
No data can be placed in the ROM 24 or the I / O interface 23, and the program fetch dedicated bus 21 is not connected to the I / O interface 25 and the resource group 26. A program cannot be placed in the I / O interface 25, and there is a drawback in that the utilization efficiency of the I / O interfaces 23, 25, the ROM 24 and the resource group 26 is poor.

The present invention has been made in view of the above points, and allows both data and programs to be accessed in both the memory whose main purpose is program access and the memory whose main purpose is data access. An object of the present invention is to provide a method of configuring a bus unit that can realize high speed.

[Means for solving the problem]

FIG. 1 shows the principle configuration of the present invention. In the figure, 30 is a bus unit and 31 is an execution unit, which are configured to operate independently. In the bus unit 30, an auxiliary program counter 32, an incrementer 33 that increments the output of the auxiliary program counter 32, and an instruction queue
An instruction register 35 to which an instruction code from the instruction queue 34 is input, and a data buffer 36 are provided.

The present invention is characterized in that the bus unit 30 is provided with a memory 40, a shared address / data bus 41, an address bus 42, and first and second connection lines 44 and 45 for the purpose of program access.

[Action]

Data address from execution unit 31 is execution unit
The address bus 38 in 31 is connected to the address bus 42 via the connecting line 43 in the bus unit 30. If the data address on the address bus 42 is the address of the area of the memory whose main purpose is program access, it is passed to the memory 40 whose main purpose is program access. It is passed to 37 and input to the I / O interface 46 and the resource group 47.

Next, the program address is output from the auxiliary program counter 32, and the processing is divided into two types depending on this program address and the previous data address.

One is the case where both the program address and the data address indicate a memory whose main purpose is program access, or both of them indicate a memory whose main purpose is data access. At this time, as shown in FIG. As in the case of the single bus shown in FIG. 5, data access and program access are alternately performed.

For example, when both the program address and the data address indicate the memory 40 whose main purpose is program access, the program address fetched from the auxiliary program counter 32 is input to the memory 40 via the address bus 42, From this, the instruction from the address designated as the input address is read and input to the instruction register 35 via the address / data shared bus 41 and the instruction queue 34.

When the above program access is completed, the address from the execution unit 31 is next transferred to the address bus 28 and the connection line 43.
And data are input to the memory 40 via the address bus 42, respectively, and the data of the designated address is read therefrom. The read data is placed on the data bus 39 via the shared address / data bus 41 and the data buffer 36.
When the above data access is completed, the program access is restarted, and thereafter, the program access and the data access are alternately repeated.

The other is a case where one of the program address and the data address described above indicates a memory whose main purpose is program access, and the other indicates a memory whose main purpose is data access. As shown in the figure, as in the case of the two-bus shown in FIG. 7, the data access and the program access are overlapped by the two buses.

For example, when the program address indicates the memory 40 whose main purpose is program access and the data address indicates the resource group 47, the program address fetched from the auxiliary program counter 32 is the address bus 42 and Resource bus 37 via connecting line 44
The instruction read from the memory 40 in the same manner as above is stored in the instruction register 35 via the address / data shared bus 41.

Further, the data address from the execution unit 31 is placed on the resource bus 37 via the address bus 38, the connection line 43, the address bus 42, and the connection line 44 in sequence, and is input to the resource group 47, from which the designated address is changed. Read data. This read data is input to the data buffer 36 via the connection line 45 and the address / data shared bus 41 in order, and is further input to the data bus 39 from this.

Therefore, in the above case, by shifting the program address and the data address placed on the resource bus 37 by a half bus state, the instructions and data placed on the shared address / data bus 41 can also be shifted by a half bus state. As shown in the figure, data access using the resource bus 37 and program access using the address / data shared bus 41 can be performed in parallel.

With this configuration, when the data address indicates a memory other than the memory 40 whose main purpose is program access, and the program address indicates the memory 40, data access and program fetch are overlapped by using different buses. Both the memory 40 whose main purpose is program access and the memory whose main purpose is data access (resource group 47 and I / O interface 46) do not have a boundary between the data area and the program area. , Both data and programs are accessible.

〔Example〕

FIG. 4 shows a block diagram of an embodiment of the present invention. In the figure,
The same parts as those in FIG. 1 are designated by the same parts, and the description thereof will be omitted. In FIG. 4, circles indicate gates,
Reference numeral 50 indicates an address buffer (ABF). When the address of 2 bytes is even, ABF50 can be accessed at one time, so it is output as it is, but when it is odd, it is output twice. Data buffers 36a and 36b respectively constitute the data buffer 36.

51 is an address out buffer (AOB), 52 is a gate that is opened only at an address indicating the area of ROM 55,
The address at this time is input to the decoder 54 through the latch 53.

Reference numeral 56 is a RAM area access trap constant generation circuit. When the program address indicates a RAM (not shown) area in the execution unit 31, it is determined that a trap constant is generated and the wrong area is accessed. It is provided to inform the user that

Reference numeral 57 is a decoder, which is a circuit for decoding whether the instruction is a 1-byte instruction or a 2-byte instruction. When the instruction is a 1-byte instruction, it outputs a 5-bit code to that effect and selects 58 from QB1.
The instruction (8 bits) is selected and output. On the other hand, when the instruction is a 2-byte instruction, the code 5 bits to that effect is output and the instruction (8 bits) fetched from the selector 58 to QB2 is selectively output.

Reference numeral 59 denotes an internal resource, which constitutes one of the resource groups 47, and 60 denotes an external resource, which is connected to the temporary register 61 via the external interface 46. Here, the external resource 60 takes 3 states from the address input until the data is taken out to the resource byte 37, while the internal resource 59 needs 2 states from the address input to the data output.
61 is provided to hold the data from the internal resource 59 for one state and output it in the third state, whereby both the internal resource 59 and the external resource 60 receive the data in the third state from the address input. Data buffer 36a, which is output and via address / data shared bus 41,
It will be input to 36b.

In the present embodiment, data access and program access can be performed at the same speed as when there are two buses using the resource bus 37 and the address / data shared bus 41 in the bus unit 30.

〔The invention's effect〕

As described above, according to the present invention, when one of the continuous data address and the program address indicates a memory whose main purpose is data access, and the other indicates a memory whose main purpose is program access, Since the data access and the program access can be performed in parallel using the two buses by shifting the bus state, the access can be executed at the same high speed as the conventional method using the two buses, and the data area It is not necessary to divide the boundary between the program area and the program area, and all the memories can be effectively used.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIGS. 2 and 3 are time charts for explaining the operation of FIG. 1, FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. FIG. 6 is a time chart of the main part of FIG. 5, FIG. 7 is a block diagram of another conventional example, and FIG. 8 is a time chart of the main part of FIG. In the figure, 30 is a bus unit, 31 is an execution unit, 32 is an auxiliary program counter, 33 is an incrementer, 34 is an instruction queue,
35 is an instruction register, 36 is a data buffer, 37 is a resource bus, 38 and 42 are address buses, 39 is a data bus, 40 is a memory, 41 is an address / data shared bus, and 43, 44 and 45 are connection lines.

Claims (1)

(57) [Claims] 1. A bus unit (30) of an auxiliary program counter (32) and an auxiliary program counter (32) of a bus unit (30) and an execution unit (31) which are made to operate independently. The auxiliary program counter which has an incrementer (33) for incrementing the output, an instruction register (35) into which an instruction code is input through an instruction queue (34), and a data buffer (36) in which data is stored, and which is continuous. In the method of configuring a bus unit in which both the output address of (32) and the address from the execution unit (31) are transferred through the resource bus (37) to alternately execute program access and data access, the bus unit (30 ), Memory (40) whose main purpose is program access, and shared address / data bus (4
1) is provided, the address bus (42) in the bus unit (30) is connected to the resource bus (37) by a first connection line (44), and the resource bus (37) is connected to the resource bus (37). It is connected to the shared address / data bus (41) by a second connection line (45), and one of the address from the execution unit (31) and the subsequent address from the auxiliary program counter (32) is the program. When the memory (40) whose main purpose is access is shown and the other one is a memory whose main purpose is data access, the bus unit (3
In the bus unit, the address / data shared bus (41) in (0) and the resource bus (37) are separately used to execute program access and data access while overlapping each other. How to configure.