JPH11312085A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently execute an SIMD(single instruction multiple data) type arithmetic operation. SOLUTION: Two-face incorporated memories 8 and 9 are provided between an SIMD type arithmetic part 21 and an outside memory 10. While one incorporated memory is connected with the SIMD type arithmetic part so that an arithmetic operation can be executed, the other incorporated memory is connected through a data transfer controller 7 with the outside memory 10 so that pack data necessary for the next arithmetic operation can be read from the outside memory 10, or pack data being an arithmetic result obtained by the arithmetic operation which is already executed by the SIMD type arithmetic part 21 can be written in the outside memory 10 by an instruction controller 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a processor.
In particular, the present invention relates to a parallel processor that executes a SIMD (Single Instruction Multiple Data) type operation in which all parallel execution operation units respond synchronously to a single instruction indicated by a single program counter.

[0002]

2. Description of the Related Art Recent microprocessors employ an architecture for multimedia. The architecture for multimedia is basically to handle data types such as pixels and audio, and to provide multimedia operation instructions. The pixel data type handled by the multimedia architecture assumes a format in which color components of pixels are packed in words. For example, in the case of a computer, pixels are represented using red (R), green (G), and blue (B) color components.

As a method of storing this pixel data in a memory, a word indicated by one address is packed in a pixel type in which R, G, and B color components are packed, or the same color component is stored in a word indicated by the same address. There are plane types and the like that are packed in order. In each case, a color component having a short bit number is packed in a word at the same address. This is generally called a pixel data type or a packed data type. Hereinafter, data of the image data type or the packed data type is referred to as packed data. Also, an instruction that can handle such packed data as an operand is
Called multimedia instructions. Basically, without separating each element (color component), with the elements packed,
It is calculated at once. Focusing on instructions, with one instruction,
A set of a source and a destination operand including a plurality of elements is designated as data, and an operation is executed. Hereinafter, this is called a SIMD type operation.

[0004] Generally, SIM by multimedia command
In the case of a processor that executes a D-type operation, data such as pixel data is stored in a memory external to the processor (hereinafter, referred to as an external memory), and an address of the external memory in which necessary data is stored is given. Data is transferred to an internal register, or conversely, data in the register is stored in an external memory.

In order to reduce access to an external memory which requires a relatively long time, a cache is provided to speed up processing.

[0006] Regarding the prior art of the processor having the above-mentioned multimedia instruction, for example, in 1996,
1st of "Latest Microprocessor Technology" by Shinichi Jimbo, Nikkei Byte PC Technology Series
Pages 96 to 208.

[0007]

In a conventional processor for executing a SIMD type operation by a multimedia instruction,
The pack data in the external memory is fetched into the register by the instruction of the program, and the S
An IMD-type operation is performed. That is, it is necessary to sequentially execute a process of taking data from an external memory into a register and a SIMD type operation. For this reason, if access to the external memory requiring a relatively long time is frequently performed, S
The IMD type operation has a problem in that the performance is not sufficiently improved due to a time loss due to access to the external memory.

As described above, a cache may be provided in order to reduce access to an external memory. In this case as well, if there is pack data to be used in the SIMD-type operation in the cache, the SIMD-type operation can be executed with relatively fast access. However, when there is no pack data to be used in the cache (at the time of a cache mishit), access to the external memory is required, and the above problem eventually occurs.

In the packed data type, since a plurality of data over two consecutive pack data are treated as one pack data because the writing and reading of data in word units are fundamental, a program Innovative and architectural ideas such as adding instructions are required.

Further, a FIFO (First Address) is provided between the external memory and the external memory.
When using an (In / First-Out) memory, it is necessary to consider the input order and output order of data used in the SIMD type arithmetic unit. Alternatively, when a two-port memory is used between the external memory and the external memory, it is necessary to transfer data from the external memory so as not to destroy the data area used for the operation in the SIMD type arithmetic unit. There is a drawback that it is necessary to manage the area to be used.

Therefore, a first object of the present invention is to provide a SIMD
An object of the present invention is to provide a processor capable of efficiently executing a type operation.

A second object of the present invention is to provide a SIMD-type operation unit with a program devising a plurality of data straddling continuous pack data as one pack data and an architectural contrivance such as adding an instruction. Without adding
The object is to provide a processor that can be easily executed.

[0013]

In order to achieve the first object, a processor according to the present invention has two internal memories between a SIMD type operation unit and an external memory. Is connected to the SIMD-type operation unit and the operation is executed, while the other internal memory is connected to the external memory and reads out the pack data required for the next operation from the external memory, or the other internal memory is already connected to the SIMD-type operation unit. The present invention is characterized in that a means for dynamically switching is provided so that the pack data, which is the result of the executed operation, can be written to an external memory.

In order to achieve the second object, a processor according to the present invention comprises a circuit for connecting a plurality of pack data read from an external memory into one new pack data, and a SIMD type operation unit. And a circuit for decomposing the pack data calculated in step (1) and using the data as pack data for storage in an external memory.

In this case, furthermore, a circuit for collecting necessary data from a plurality of pack data read from the external memory and forming one pack data, and a pack data which is a result calculated by the SIMD type arithmetic unit are stored in the circuit. Alternatively, new pack data may be used so as to be pack data for storage in an external memory, and writing control may be performed for each data in the pack data.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a processor according to the present invention will be described in more detail with reference to the drawings. In the following description, the same reference numerals indicate the same or similar components. In the second and subsequent embodiments, differences from the first embodiment will be mainly described.

<First Embodiment of the Invention> FIG. 1 is a block diagram showing an embodiment of a processor according to the present invention. In FIG. 1, reference numeral 11 indicates a processor,
The processor 11 includes a SIMD-type operation unit 21 including an operation unit and a register 2 to which all the parallel execution operation units 3 to 6 synchronously respond to a single instruction, a SIMD-type operation unit 21 and an external Internal memories 8 and 9 for exchanging pack data with memory 10, data transfer controller 7 for transferring pack data between external memory 10 and internal memories 8 and 9, SIMD type operation unit 21 and data transfer It comprises an instruction controller 1 for issuing an instruction to the controller 7. A feature of the processor 11 of the present invention is a portion surrounded by a dotted line in FIG.

The instruction controller 1 of the processor 11 first transfers the pack data used for the operation in the SIMD type operation unit 21 from the external memory 10 to the internal memory 9 via the buses S3 and S3.
4 to the data transfer controller 7 via the signal line S2. In accordance with this instruction, the data transfer controller 7 operates to transfer data from the designated area of the external memory 10 to the internal memory 9.

Next, the instruction controller 1 stores the internal memory 9 in S
At the same time as connecting to the IMD type operation unit 21 via the bus S5, the built-in memory 8 is connected to the data transfer controller 7 via the bus S4, and from the instruction controller 1 to the data transfer controller 7 via the signal line S2. An instruction to transfer the pack data in the external memory 10 to the internal memory 8 is issued. This allows
The data transfer controller 7 operates to read the pack data from the external memory 10 and write the pack data to the internal memory 8. At this time, the built-in memory 9 stores the SIM
Since it is connected to the D-type operation unit 21, the pack data is transferred from the built-in memory 9 to the register 2 in accordance with the instruction issued by the instruction controller 1 through the signal line S1, and the operation is performed by the parallel execution operation units 3 to 6. Behave as if it were. In addition, according to an instruction from the instruction controller 1 through the signal line S1, the operation is performed such that the pack data as the operation result in the register 2 is written into the built-in memory 9.

FIG. 2 is an explanatory diagram showing an outline of the above operation. The operation shown by the block 200 is the operation of the external memory 1
The data transfer controller 7 controls the transfer of the pack data in the area 101 in the area 0 and the pack data in the built-in memory 8, while the pack data in the built-in memory 9 is connected to the SIMD-type operation unit 21 to perform instruction control. Operation and transfer control are performed according to an instruction from the device 1.

The operation shown by the block 201 is to control the transfer of the pack data in the area 102 in the external memory 10 and the pack data in the internal memory 9 by the data transfer controller 7, while the pack data in the internal memory 8 is It is connected to the SIMD type operation unit 21 and is operated and transferred in accordance with an instruction from the instruction controller 1. That is, the block 20
A feature of the present invention is that the operation indicated by 0 and 201 can be switched and operated by the instruction of the instruction controller 1.

<Embodiment 2> FIG. 3 is a block diagram showing another embodiment of a processor according to the present invention. Here, the width of the data bus S3 that interfaces with the external memory 10 is 16 bits,
The pack data in 0 is also in units of 16 bits. SIMD
Each of the parallel operation calculators 3 to 6 in the type calculation unit 21
When an 8-bit operation is executed, the SIMD type operation unit 2
The pack data to 1 is preferably 32 bits.

In the data transfer controller 7 of this embodiment, the 16-bit width packed data read from the external memory 10 via the bus S3 is stored in the internal memory 8 or the internal memory 9 via the bus S4. When transferring, 2
A function of concatenating the 16-bit pack data and transferring it as a 32-bit pack data unit; and decomposing the 32-bit pack data read from the internal memory 8 or the internal memory 9 into two 16-bit pack data units Data linking / decomposing unit 71 having a function of transferring data as
Is provided. The transfer control unit 72 includes a data connection / decomposition unit 71
It controls the transfer of 32-bit packed data between the internal memory 8 and the internal memory 8. Thus, the two 16-bit packed data read from the external memory 10 can be written to the built-in memory 8 or the built-in memory 9 as 32-bit packed data. Conversely, it is also possible to decompose the 32-bit pack data read from the internal memory 8 or the internal memory 9 into two 16-bit pack data in the external memory 10 and store them.

In this embodiment, the external memory 1
Although the width of the data bus S3 of the interface with 0 is 16 bits and the width of the data bus of the interface with the built-in memories 8 and 9 is 32 bits, the processor of the present invention is not limited to this bit width. Needless to say, it is possible to correspond to the bit widths of any of the above external memories and internal memories.

<Third Embodiment of the Invention> FIG. 4 is a block diagram showing still another embodiment of the processor according to the present invention. In the present embodiment, a byte boundary processing unit 73 is further provided in the data transfer controller 7 of FIG. 3 shown in the second embodiment. Here, the width of the data bus S3 that interfaces with the external memory 10 is 16
It is assumed that two packs of 8-bit data constitute one pack data in the external memory 10.

The unit for reading the pack data from the external memory 10 is the unit for reading from the head of the word,
5 or 9, for example, as shown in FIG. 5A, data (Data00) from the upper byte of the word starting at address “00004” to the lower byte of the word starting at address “0000A” in the external memory 10.
004-Data0000B) and read out the same FIG.
As shown in FIG.
When the read data is transferred from “00” to “10007”, the data can be read by the operation described in the second embodiment.
“DataXXXXXX” indicates data in the address “XXXXXX” of the external memory 10.

However, when it is necessary to read the pack data from the external memory 10 from the data in the lower byte (8 bits) of the word and convert it into 32-bit pack data, for example, FIG. As shown in the figure, the data of the lower byte (8 bits) of the word starting from the address "00004" of the external memory is cut out and combined with the upper byte (8 bits) of the word starting from the next read address "00006" to form 16 bits. A circuit which is input to the data linking / decomposing unit 71 for processing 16-bit / 32-bit data is the byte boundary processing unit 73 shown in FIG. Conversely, 16 bits / 3
The byte boundary processing unit 73 performs an operation of controlling the writing of the output from the data linking / disassembling unit 71 that performs 2-bit data processing so as to correspond to the 16-bit packed data in the external memory 10.

Further, the byte boundary processing unit 73
The processing is performed also for the transfer shown in FIG. That is, FIG. 7 shows the addresses “00000”, “00002”, and “0000” of the external memory 10 shown in FIG.
Only the data in the upper byte (8 bits) of each word starting from 4 ″,... Is transferred to the internal memory 8 or the internal memory 9 as shown in FIG. Is the case.

The byte boundary conversion unit 73 includes the external memory 10
It is possible to cut out a portion having an arbitrary bit width from the 16-bit width packed data and to embed data in an arbitrary bit portion.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. Obviously you can get it.

[0031]

According to the processor of the present invention, the transfer of data to and from the external memory and the SIMD-type operation can be executed in parallel, so that the SIMD-type operation unit can be operated efficiently. And speeding up the processing.

The SIMD is designed to use a plurality of data straddling continuous pack data as one pack data, and to improve the architecture such as adding instructions.
It can be easily executed in the data transfer controller without adding to the type operation unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a processor according to the present invention.

FIG. 2 is an explanatory diagram showing an outline of the operation of a processor having the configuration shown in FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the processor according to the present invention.

FIG. 4 is a block diagram showing another embodiment of the processor according to the present invention.

FIG. 5 is an explanatory diagram showing an example of data transfer between an external memory and a built-in memory of the processor shown in FIG. 4;

6 is an explanatory diagram showing another example of data transfer between an external memory and a built-in memory of the processor shown in FIG. 4;

FIG. 7 is an explanatory diagram showing another example of data transfer between an external memory and a built-in memory of the processor shown in FIG. 4;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Instruction controller, 2 ... Register, 3-6 ... Parallel execution arithmetic unit, 7 ... Data transfer controller, 8, 9 ... Built-in memory, 10
... external memory, 11 ... processor, 21 ... SIMD type operation unit, 71 ... data connection / disassembly unit, 72 ... transfer control unit,
73 ... Byte boundary processing unit

Claims (3)

[Claims] 1. A SIM in which all parallel execution operation units synchronously respond to a single instruction indicated by a single program counter, and perform parallel processing of a total of N bits.
In the D-type processor, two built-in memories and a data transfer controller for transferring data to and from an external memory with a bus width of M bits (M <N) are provided. The connection destination of the two built-in memories can be dynamically switched so that the other built-in memory is connected to the parallel execution operation unit when connected to an external memory via a controller. Features processor. 2. A method for transferring data to and from an external memory, wherein the bit width is M bits, the bit width for transferring data to an internal memory is N bits, and a plurality of M bits are connected in the data transfer controller. A circuit that transfers data to and from an external memory in units of N-bit data, and a circuit that separates N-bit data and transfers data to and from the external memory in units of a plurality of M bits. The processor according to claim 1, further comprising: 3. The minimum unit of data exchange with an external memory is 8
The bit width for transferring data to and from the external memory is M bits, which is K times 8 bits, and the bit width for transferring data to and from the internal memory is N bits. Data is transferred from the external memory to the internal memory. When doing, M
A function that generates a necessary part from bits in 8-bit units and a function that writes data from the internal memory to a required 8-bit unit position on the external memory when transferring data from the internal memory to the external memory 3. The processor according to claim 2, further comprising a byte boundary conversion circuit having the following configuration: