JP2000047935A - High speed memory access processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the data transfer by reducing the load on a processor required for data transfer processing between memories. SOLUTION: This device is provided with a means for updating an address pointer part for pointing the leading address of the transfer destination and a range instructing part 7 for showing the range of data stored in a memory 9 to be transferred with the transfer destination address and transfer data amount received from a processor 1 in the case of transferring the said data from a transfer source address to the transfer destination address for the desired data amount and without actual data transfer, transfer to the transfer destination is completed only by setting the address pointer part and range instructing part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a technique for transferring data between memories.

[0002]

2. Description of the Related Art In computer systems, data transfer between memories is frequently performed.
In accordance with a program instruction, the processor reads data in the memory once into an internal register or the like with a load instruction, and writes the data read into the internal register into the memory with a store instruction.

[0003]

As described above, in the conventional information processing apparatus, at the time of data transfer, the processor reads data in the memory once into an internal register or the like by a load instruction and then reads the data into the internal register. It is configured to write data to memory with a store instruction,
There is a problem that the load on the processor required for the data transfer processing in the memory is large.

In Japanese Patent Application Laid-Open No. 4-115335, the memory space is divided into a plurality of blocks, and the positions of the blocks are registered as real memory numbers, and the CPU refers to the real memory numbers. An address conversion table for registering a reference block number to be registered and a memory address (logical address) from the CPU are searched, and a reference block number to which the memory address belongs is searched and converted to an actual block number corresponding to the reference block number. A conversion method has been proposed which includes an address conversion device for notifying the memory of the actual block number via an address bus, and which does not require a CPU to perform a memory transfer process when converting a memory address. In this conventional method,
For example, when there is an unused block having a low real address number, an unused real address number is set in the address conversion table at a position corresponding to a reference block number located at a high address as viewed from the CPU. Can be assigned to a higher reference block number as viewed from the CPU.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to reduce the load on a processor required for data transfer processing between memories and to provide a high-speed memory access for speeding up data transfer. An object of the present invention is to provide a processing device.

[0006]

To achieve the above object, the present invention provides a means for updating an address pointer indicating a transfer destination address in a memory with the transfer destination address when transferring data in the memory. And the transfer processing to the transfer destination is completed only by changing the address pointer value without actually transferring the data from the transfer source to the transfer destination.

According to the present invention, when transferring a desired amount of data stored in a memory from a transfer source address to a transfer destination address, an address pointer unit pointing to the start address of the transfer destination and the transferred data A means for updating a range indicating unit indicating a range of the transfer destination address and the transfer data amount received from the processor, without involving actual data transfer, the address pointer unit,
Then, the transfer process to the transfer destination is completed only by setting the range indicating section.

[0008]

Embodiments of the present invention will be described. When transferring data in a memory to another memory area, the high-speed memory access processing device according to the present invention converts an address indicating a data storage location into a transfer destination address instead of transferring the data. By doing so, the processor does not need to move the data in the memory from the transfer source to the transfer destination, thereby achieving high-speed memory access.

More specifically, in a preferred embodiment of the present invention, referring to FIG. 1, when data stored in a data section (8) of a memory is transferred to another area, a processor section (1) is used. ), The address before transfer, the address of the transfer destination, and the transfer data amount are converted into an address conversion unit (5)
Pass to. The address conversion unit (5) determines the data transfer process, and rewrites the address unit (6) and the range designation unit (7) with the transfer destination address and the transfer data amount received from the processor unit, respectively. , Data transfer becomes possible. Hereinafter, description will be made in accordance with embodiments.

[0010]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 1, one embodiment of the present invention includes a processor unit 1 and a memory unit 9, wherein the memory unit 9 includes an address conversion unit 5, an address unit 6, a range designation unit 7,
A data section 8.

The processor 1 and the address converter 5 are connected by a unidirectional address signal line 2, a transfer control line 3, and a bidirectional data signal line 4.

The processor unit 1 transmits a position where memory data is stored and a transfer destination address to an address signal line 2.
To the address conversion unit 5. Processing of data transfer in the memory is controlled by the transfer control line 3 to the address converter 5.
Pass to.

The processor unit 1 transfers the amount of data to be transferred from the data signal line 4 to the address conversion unit 5 when performing data transfer in the memory unit 9.

The address conversion unit 5 includes an address signal line 2,
From the information obtained from the transfer control line 3 and the data signal line 4, the address and data range of the data stored in the memory are determined.

The address section 6 indicates a position where data in the memory is stored. The range designation section 7 indicates the width of data stored in the data section 8 in the memory section 9. The data section 8 stores data.

The operation of one embodiment of the present invention will be described. When data in the memory area is transferred from the processor unit 1 to another area, the processor unit 1 sends a source address and a destination address to the address conversion unit 5 via the address signal line 2.

Further, the fact that the data transfer is in the data section 8 (in the memory area) is transmitted from the processor section 1 via the transfer control line 3 to the address conversion section 5.

Further, the data signal line 4
The data transfer amount in the data section 8 is sent to the address conversion section 5 via

In the address conversion unit 5, the address signal line 2
And obtained via the transfer control line 3 and the data signal line 4,
The address section 6 indicating the position of the data stored in the data section 8 is changed from the transfer source address to the transfer destination address based on the transfer source address, the transfer destination address and the data transfer amount.

The address conversion unit 5 replaces the data width obtained through the data signal line 4 with the range specification unit 7 indicating the width of the data stored in the data unit 8.

As a result, the address section 6 and the range specifying section 7 indicate the transfer destination address and the data range, respectively, indicating that the data has been transferred in the memory.

As described above, in one embodiment of the present invention,
Each time data is transferred between memories, the address unit 6
Then, the contents of the address range indicating section 7 are updated with the transfer destination address and the transfer data amount. FIG. 1 schematically shows a state in which data transfer between memories is performed three times, and a transfer destination and a transfer data amount in the data section 8 are respectively indicated by an address section 6 and a range indicating section 7. Instructed by.

When the processor unit 1 executes the reference instruction of the memory unit 9 (the transfer control line 3 indicates reading), the access address signal transmitted from the processor unit 1 to the address signal line 2 is transmitted to the address unit. 7, the data stored in the memory unit 9 is accessed by the address pointer of the address unit 7 and passed to the processor unit 1 via the data signal line 4. That is, the program instruction executed by the processor unit 1 is:
It is possible to perform exactly the same processing as when data transfer (movement) on the memory is performed as usual.

Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 2, the second embodiment of the present invention includes a data transfer unit 10 in place of the address unit 6 and the range designation unit 7 of the embodiment shown in FIG. The data section 8 is connected by a data line 11. In the second embodiment of the present invention, the data stored in the data section 8 is transferred to the data line according to the transfer source address, the transfer destination address and the data transfer amount obtained from the address conversion section 5 by the data transfer section 6. The data is transferred from the transfer source address to the transfer destination address via the address 11.

In the second embodiment of the present invention, the data transfer in the data section 8 of the memory section 9 is performed without the processing of the processor section 1, so that the load on the processor 1 is reduced.

[0026]

As described above, according to the present invention,
When transferring data in the memory to another memory area, by reducing the load on the processor by changing the address and the data range pointing to the data storage location without passing through the processor, This has the effect. For this reason, according to the present invention, in memory transfer of a large amount of data, processing is completed by converting an address indicating a data storage location into a transfer destination address, and performance can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a high-speed memory access processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a high-speed memory access processing device according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor part 2 Address signal line 3 Transfer control line 4 Data signal line 5 Address conversion part 6 Address part 7 Range specification part 8 Data part 9 Memory part 10 Data transfer part 11 Data line

[Procedure amendment]

[Submission date] May 17, 1999 (1999.5.1
7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

[0006]

In order to achieve the above object, the present invention provides a method for transferring data stored in a memory.
To the desired amount of data transferred from the transmission source address to the destination address
Pointer to the start address of the transfer destination
Unit and a range indicating unit indicating the range of the data to be transferred
Is the transfer destination address and transfer received from the processor.
Means for updating with the data amount, the address pointer unit and the range pointer without actual data transfer.
The transfer processing to the transfer destination is completed only by setting the display section .

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

[0007] The present invention, position of data stored in the memory
And an address pointer for instructing the location, and stored in the memory.
And a range designating section indicating the range of data to be
The data stored in the memory from the processor.
Source address, destination address, and transfer data
The address pointer part, and
Address to the received forwarding address
And the range designating unit stores the received transfer data.
Address translation unit with means for setting
The address pointer unit and the range designating unit are
By indicating the data transfer destination address and data range,
The transfer process is completed without actual data transfer in the memory .

Claims (4)

[Claims] When transferring data stored in a memory from a transfer source address to a transfer destination address in a desired amount, an address pointer indicating a transfer destination address in the memory is updated with the transfer destination address. A high-speed memory access processing device comprising means for completing transfer processing to a transfer destination only by changing the address pointer value without actually transferring data from a transfer source to a transfer destination. 2. When transferring a desired amount of data stored in a memory from a transfer source address to a transfer destination address, an address pointer portion pointing to a start address of a transfer destination and a range of the transferred data are set. The range indicator shown
Means for updating with the transfer destination address and the transfer data amount received from the processor, and performing the transfer processing to the transfer destination only by setting the address pointer section and the range indicating section without actual data transfer. To complete,
A high-speed memory access processing device, characterized in that: 3. An address pointer unit for indicating a position of data stored in a memory, and a range designating unit for indicating a range of data stored in the memory. Receiving the transfer source address, the transfer destination address, and the transfer data amount of the data, changing the address pointer section from the transfer source address to the received transfer destination address, and changing the range specifying section to the received transfer address. An address conversion unit having means for setting a data amount, wherein the address pointer unit and the range designation unit indicate an address and a data range of a data transfer destination, so that actual data transfer in the memory is performed. A high-speed memory access processing device for performing a transfer process without any accompanying processing. 4. A method according to claim 1, further comprising the steps of: sending a source address, a destination address,
Data transfer means for receiving the transfer data amount and transferring the data of the transfer source address stored in the memory to the transfer destination address by the transfer data amount. Processing equipment.