JPS62147545A - Processing system for transfer instruction of information processor - Google Patents

Abstract

PURPOSE:To produce the transfer data with high efficiency by providing a shifter control part which can decide the number of shifts based on the difference between both data areas and a mechanism which can regard the partial data width as four bytes. CONSTITUTION:A shifter control part 1-10 gives the arithmetic output of an arithmetic logic unit 1-4 to a shift arithmetic unit 1-3 as the shift number, a store data register 1-12 can decide whether only the upper half, the lower half or both upper and lower halves are set when the data is set from a certain register and a shifter input part 1-9 can combine the upper data at one side and the lower data at the other side and supply them to the unit 1-3 are provided to the titled system. Thus the executing time of a transfer instruction can be shortened without increasing the hardware quantity so much in case the transfer transmitter data area address and the transfer receiver data area address overlap with each other by a difference of eight bytes or less.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a transfer command processing method in an information processing device, and particularly to a transfer command processing method suitable for when the transfer source data area and the transfer destination data area of the transfer command overlap. Regarding the method.

[Background of the invention]

In a transfer command, if the transfer source data area and transfer destination data area overlap, the store operation and reference to the main memory overlap, slowing down the execution time.

The case in which the difference between the two data areas is 1 byte is often used in programs, so it was possible to process it at high speed even with conventional machines, but other overlap cases were not taken into account. In addition, as a description of the specific operation of the transfer command, IBM System 1570
Principles of Operation (IBM Systems)
stem/ 370 Pr1nciples of Op
[Object of the Invention] An object of the present invention is to reduce the execution time of a transfer instruction when the transfer source data area and the transfer destination data area are overlapping with a difference of 8 bytes or less. The purpose is to provide a processing method that shortens the processing without significant increase.

[Summary of the invention]

In a transfer command, if the transfer source data area and transfer destination data area overlap with a difference of 8 bytes or less,
As long as the first 8 bytes of data in the transfer source data area are known, all transfer data can be generated without actually referring to the main memory. However, if the hardware processing system is not designed for 8 bytes of data, For example, when the difference between both data areas is 5.5 or 6.7 bytes, transfer data cannot be efficiently generated and instruction execution becomes slow. By adding a shifter control unit that can determine the number of shifts based on the number of shifts, and a mechanism that partially treats the data width as 4 bytes, it is possible to efficiently generate transfer data.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. The arithmetic unit 1 reads the microprogram one step at a time from the control storage device 1-1, decodes it in the arithmetic control unit 1-2, and executes shift arithmetic units 1-3, arithmetic logic units 1-4, . and controls each register to proceed with the process. The arithmetic device 1 transfers data to and from the main storage device 3 via the system control device 2 in units of 8 bytes. The registers other than the 4-byte store address registers 1-5 are 8 bytes in size, and include shift operation units 1-3, ] logical operation units 1-4.
can operate on 8 bytes of data. Arithmetic logic unit 1-
4 inputs register Aj-6 and register B1-7,
Set the operation result in register C1-8. The input of the shift calculator 1-3 is controlled by the shifter input section 1-9, and whether register A1-6 or register B1-7 is input depends on the upper 4 bytes and lower 4 bytes of the input data. are selected separately. The calculation is controlled by a shifter control section 1-10. The shifter control unit 1-10 has a register C1-8.
It is also possible to control the calculation by using a value obtained by multiplying the value of the lower 3 bits by 8 as the shift number. The calculation result is in register DI-1
Set to 1. For store data registers 1-12, when setting data from registers c1-8 or register DI-11, it is possible to select whether to set only the upper 4 bytes, only the lower 4 bytes, or set all 8 bytes. . The data in the store data registers 1-12 is transferred to the system controller 2 together with the data in the store address registers 1-5, and when the microprogram specifies a store operation, the data is written into the main memory 3. The data read from the main memory device 3 is set in the memory data registers 1-13 by the system control device 2, and the registers A1-6.
Data is transferred to registers B1-7.

The system control device 2 reads instructions from the main storage device 3, decodes them, sets necessary data in registers, and then starts the microprogram.

A case will be described below in which the instruction is a transfer instruction, the destination data area is at a higher address than the source data area, and the two areas overlap.

In this case, the system controller sets data as shown in FIG. 2 and starts the microprogram. FIG. 5 shows the operation of the microprogram. Steps 301-503
is preprocessing, and in addition to what is shown in the figure, it is also necessary to check whether the difference between the transfer source data area address and the transfer destination data area address is 8 bytes or less, but this is omitted.

Here, explanation will be given assuming that the difference between the addresses of both areas is 5 bytes. At step 601, the difference between the addresses of both areas, that is, 5, is set in register C. In step 505, the upper store data is set, and in step 5
The lower store data is set at 04, and the store operation is specified when all 8 bytes of store data are available. In step 605, the upper half of the next 8-byte store data is set, and at this time, the upper 5 bytes of register A are equal to the lower 5 bytes of register B. Namely.

This is register A and register B in step 303.
By repeating steps 305 and 304, 8 bytes of data are created one after another. Steps 305 and 304 are executed as many times as necessary while increasing the store address register by 8.

If the difference between the transfer source data area address and the transfer destination data area address is 2 or 30, the difference between the transfer source data area address and the transfer destination data area address is 2 or 6 bytes during preprocessing.
After arranging two byte data, processing can be performed in the same way as if the difference between both areas is 4 or 6.

As explained above, according to the present invention, 8-byte data can be successively generated and stored in the main memory in two cycles.

〔Effect of the invention〕

According to the present invention, the execution time of a transfer instruction when the transfer source data area address and the transfer destination data address overlap with a difference of 8 bytes or less can be shortened without significantly increasing hardware.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of an arithmetic unit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of an initial state, and FIG. 3 is an explanatory diagram showing a processing procedure of a microprogram. DESCRIPTION OF SYMBOLS 1... Arithmetic device, 1-1... Control storage device, 1-2... Arithmetic control unit, 1-3... Shift operator, 1-4... Arithmetic logic operator, 1- 5...Store address register, 1-6...Register A, 1-7...Register B. 1-8...Register C, 1-9...Shifter input section,
1-10...Shifter control unit, 1-11...Register D. 1-12...Store data register, 1-13...
Memory data register, 2... system control device, 3... main storage device.

Claims (1)

[Claims] 1. In an arithmetic unit configured mainly of one or more arithmetic logic processors, shift processors, and registers controlled by a microprogram, the calculation output of the arithmetic logic processor is used as a shift number in a shifter. When setting data from a certain register, there is a store data register that allows you to select whether to set only the upper half, only the lower half, or both the upper and lower half. A transfer command processing method in an information processing device, characterized by having a shifter input unit that can combine upper data and the other lower data and input it to a shift calculator.