JP2982129B2 - Micro program controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram controller, and more particularly, to controlling the processing of microinstructions in a plurality of execution cycles by an instruction control word read from a control storage in one access unit. The present invention relates to a microprogram control device for performing

[Conventional technology]

In a microprogram control type processing device,
The micro-instructions stored in the control memory are read one by one, and the operation of each instruction execution unit in the processing device based on the micro-instructions is repeated. Since the operation speed of the processing device is the repetition operation time, the repetition operation is performed at high speed in order to increase the operation speed.

For this reason, in the processing device of the microprogram control system, the reading of the microinstruction to be executed next is performed during the execution of a certain microinstruction by operating the reading of the microinstruction and the execution of the instruction processing independently. As a result, read control is performed such that the apparent micro instruction read time is zero. However, if the access time of the memory used for the control storage is later than the operation time of the instruction execution unit, the read time of the microinstruction will be on the surface from the end of execution of one microinstruction to the start of execution of the next microinstruction. As a result, there is a problem that an extra execution cycle time is required and the processing speed of instruction processing is reduced.

As one method for solving this problem, there is known a method of a microprogram control system in which microinstructions for a plurality of execution cycles are simultaneously read from control storage.
According to this method, even if the read cycle of the microinstruction is longer than the execution cycle of one microinstruction, if one control storage access is possible in the execution cycle of a plurality of microinstructions, the microinstruction In execution, invalid cycles can be prevented from occurring. However, the number of microinstructions to be read at the same time is determined according to the machine cycle, the access time of the control storage, and the like.

FIG. 4 is a time chart for explaining an example of a microprogram control system for simultaneously reading such microinstructions for a plurality of execution cycles. The time chart of FIG. 4 shows an example in which two micro-instructions are read in one access unit to execute the instruction processing. Referring to FIG. 4, description of an example in which two micro-instructions, which are such continuous execution units, are simultaneously read and the processing of the micro-instructions is performed will be continued. Micro instruction A, which is the execution unit
Then, a set of microinstructions B is read from the control storage, and the microinstruction A is executed in the third machine cycle, and the microinstruction B is executed in the next fourth machine cycle. At this time,
The next two consecutive micro-instructions C and D are read out, overlapping with the execution of the micro-instructions A and B. Then, in the next fifth machine cycle after the completion of the microinstruction B in the fourth machine cycle, the microinstruction C already read is executed, and then the microinstruction D is executed. At this time, the execution of the microinstruction C and the microinstruction D is overlapped, and the next two consecutive microinstructions E and F are read. In this way,
Each microinstruction can be executed successively, and invalid cycles on the instruction execution cycle can be eliminated. In such a method, the micro-instructions for two execution cycles must be read simultaneously from the control storage by one access, so that the bit width of the instruction control word becomes large,
There is a problem that the storage capacity of the control storage, the capacity of the control storage data register, and the like increase.

To solve such a problem, for example, a specific field of the microinstruction is given a double meaning, and one of the fields having a double meaning is used according to the instruction data of the other field. Thus, a microprogram control method in which the number of fields is reduced has been proposed. The central processing unit described in Japanese Patent Application Laid-Open No. 57-161940 is an example of such a microprogram control method. In this microprogram control type central processing unit, a control word of a microinstruction is provided with a branch control field and an operation control / branch address field. The information in the address field is used as a branch address, and in cases other than branching, it is used as operation control information. Thereby, the control word of the microinstruction is effectively used, and the bit width of the control storage is reduced.

[Problems to be solved by the invention]

By the way, in the microprogram control method as described above, a control word of a microinstruction is provided with a branch control field and an operation control / branch address field. The information in the branch address field is used as a branch address, and in cases other than a branch, it is used as operation control information. Therefore, the control word of the microinstruction can be effectively used, and the bit width of the control storage can be reduced.

However, in this case, the information in the operation control / branch address field of the control word of the microinstruction of one access unit is also used as the branch address information or the operation control information. The arithmetic control cannot be performed, and when the arithmetic control is similarly performed, the execution control for branching cannot be performed, and there is a problem that the execution efficiency in executing the microinstruction is reduced.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprogram control device that minimizes a decrease in execution efficiency of microinstruction execution control and reduces a bit width of a control word of a microinstruction.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

To achieve the above object, in the present invention, a control word of a microinstruction stored in a control memory is read,
In a processing device which performs processing by a microprogram control method for controlling a microinstruction, a control word provided with a field control unit and a plurality of control field units is read from a control storage in one access unit, and a plurality of execution cycles are executed by the control word. A control circuit for controlling, and a plurality of execution units operable for each execution cycle, selecting an execution unit to be operated in each control field unit based on the contents of a field control unit of a control word, and executing each execution unit. It is characterized in that a unit execution cycle instruction is issued.

More specifically, the control word includes a control circuit for controlling an execution cycle of two machine cycles by a control word read in one access unit from a control memory, and a plurality of execution units operable for each execution cycle. A control unit and a plurality of control field units, wherein the control field unit is divided into one or more control fields operating in a first execution cycle and one or more control fields operating in a second execution cycle; Of the control fields operating in two execution cycles, a predetermined specific field performs control to be used as branch control information and branch address information in the first execution cycle when branching is instructed by the field control unit, If the branch is not instructed, the control used as the control field in the second execution cycle And performing.

Further, when the branch is instructed by the field control unit and the branch is not taken, the control according to the remaining control fields other than the specific field among the control fields for the second execution cycle is performed in the second execution cycle. It is characterized by.

[Action]

According to the above means, there are provided a control circuit for controlling a plurality of execution cycles by a control word read from the control storage in one access unit, and a plurality of execution units operable for each execution cycle. The control word of the microinstruction is provided with a field control unit and a plurality of control field units. The control field unit is divided into, for example, one or more control fields operating in a first execution cycle and one or more control fields operating in a second execution cycle, and based on the contents of the field control unit, An execution unit operated in each control field unit is selected, and an execution cycle instruction of each execution unit is issued.

Thus, in the execution control of the microinstruction, the execution unit to be operated in each control field unit is arbitrarily selected and the execution cycle of the execution unit is instructed based on the contents of the field control unit. Control can be performed efficiently. Further, since the control field portion can be selectively used for the field control portion depending on the content, the bit width of the control word of the microinstruction can be reduced.

For example, when the predetermined specific field among the control fields operating in the second execution cycle performs a branch according to the instruction of the field control unit, the control field unit controls the control field to use as branch control information and branch address information. When no branch is performed, control is performed in the second execution cycle to use the control field.

That is, in a preferred embodiment, a control circuit for controlling an execution cycle of two machine cycles by a control word read from the control storage in one access unit, and a plurality of execution units operable in each execution cycle are provided. One field control unit and a plurality of control field units are provided for the control word. The control field unit includes one or more control fields operating in a first execution cycle and a second control field.
Is divided into one or more control fields that operate in the execution cycle. Then, among the control fields operating in the second execution cycle, a predetermined specific field is controlled to be used as branch control information and branch address information when branching is performed according to an instruction of the field control unit. When the branch is not performed, the control is performed so as to be used as a control field in the second execution cycle.

Thus, when the microinstruction does not involve a branch, the control fields read from the control storage are operated by the execution unit in the first execution cycle and the second execution cycle, respectively, and the next address is the current control storage address. The next value of is selected. Execution control is a control that selects each execution unit by sequential processing and performs processing.
Processing proceeds.

When a branch is involved, the first execution cycle operates according to the information in the control field for the first execution cycle, and is indicated by a specific field defined in the control field for the second execution cycle according to an instruction of the field control unit. Branch control is performed based on the branch control information and the branch address information. When the branch is taken, the control storage is read from the address indicated by the branch address information, and execution control for continuing the processing is performed. When the branch is not taken, the remaining fields not used for the branch control information and the branch address information among the control fields for the second execution cycle are operated by the execution unit in the second execution cycle.

Since such an execution control operation is performed, the control field is controlled in the second execution cycle when the branch is not taken, but the control field is not restricted when the branch is taken, so that the execution efficiency of the microinstruction execution control is reduced. It can branch without lowering. As a result, it is possible to reduce the bit width of the control word while minimizing the decrease in the execution efficiency of the microinstruction including the branch.

〔Example〕

Hereinafter, an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram of a processing device by a microprogram control device according to one embodiment of the present invention. First
In the figure, 1 is a control storage unit, 2 is a control storage data register, 3 is a field control circuit unit, 4 is an execution cycle control unit, and 5 to 7 are selectors. Reference numerals 8 to 10 denote execution units for executing microinstructions in each field, 11 to 12 denote switchers, and 13 denotes a branch control unit. 14 is a selector, 15 is a control storage address register, and 16 is an incrementer.

One control word, which is one access unit of the control storage unit 1, is used by dividing each field in the control storage data register 2. That is, one X field which is a field control unit, and six control fields which are a control field unit, that is, a C0 field, a F0 field, and an L0 field of a micro instruction for the first execution cycle, and a second execution cycle For micro instruction
It is divided into C1 field, F1 field and L1 field for use. The control word read out from the control storage unit 1 in units of one access and latched in the control storage data register 2 is used when the execution cycle is the first execution cycle.
According to the instruction from the execution cycle control unit 4, the C0 field, F0 field, and L0 field of the control storage data register 2 are selected by the selectors 5, 6, and 7, respectively, and sent to the execution units 8, 9, and 10 of each field. Similarly, in the second execution cycle, the selectors 5, 6, and 7 respectively specify the C1 field, the F1 field, and the L1
The field is selected and sent to the execution units 8, 9, 10.

If micro-instructions are processed sequentially without branching,
The control storage address stored in the control storage address register 15 is sequentially increased by the incrementer 16, and the next control word is read from the control storage unit 1 in accordance with the control storage address of the control storage address register 15.

When the microinstruction includes a branch, the field control circuit 3 operates according to the X field information of the control storage data register 2,
The information in the F1 field is taken into the branch control unit 13 through the switch 11 as branch control information (T field). When the branch is taken, the information of the L1 field is taken into the control storage address register 15 via the switch 12 and the selector 14 as the branch address (B field). As a result, the read address data of the next control word becomes the branch address of the B field, and the control word of the control storage unit 1 is read with this address data, and the branch is performed.
If the branch is not taken, the branch address of the B field is not taken into the control storage address register 15 and the selector
The next address data incremented from the incrementer 16 via 14 is taken into the control storage address register 15. In this case, the second execution cycle operates next, and only the C1 field of the second execution cycle control field is sent to the execution unit 8.

FIG. 2 is a diagram showing an example of a control word for explaining execution control of a microinstruction accompanied by branch control. FIGS. 3a and 3b are time charts for explaining execution control of a microinstruction accompanied by branch control.

The control word of the microinstruction is as shown in FIG.
An example in which the execution of microinstruction processing is controlled by these control words stored in addresses N0 to N2, N5 to N6, and B0 to B1 of the control storage unit 1 will be described.

Please refer to FIG. 3a. In machine cycles 1 and 2, the address data N0 of the control storage address register 15
The read operation from the control storage unit 1 is performed, and the execution control of the read control word C0F0L0C1F1L1 is controlled by the machine cycle 3,
Done at 4. In the machine cycle 3, the execution cycle control unit 4 outputs a logical "0" signal to indicate that the machine cycle 3 is the first execution cycle, and controls the selectors 5, 6, and 7 to execute the first execution cycle. The execution units 8, 9, and 10 execute the control field C0F0L0. In the next machine cycle 4, the execution cycle control unit 4 outputs a logical "1" signal to indicate that the machine cycle 4 is the second execution cycle. Therefore, the second execution cycle is controlled by the selectors 5, 6, and 7. Execution of each control field C1F1L1 of the cycle is performed by the execution units 8, 9, and 10. At this time, in the machine cycles 3 and 4, the address data of the control storage address register 15 is updated to the address N1, and the next control word is read from the control storage unit 1 by this address data N1. The execution control of the second control word C2F2L2C3T0B0 read in this read operation is performed in the next machine cycle 5,
Done at 6.

Since the fact that the second control word C2F2L2C3T0B0 includes a branch is indicated by the logic "1" of the X field indicating the field control, the machine cycles 5, 6
In, the field control circuit section 3 outputs a logical "1" signal and controls the execution of the second control word C2F2L2C3T0B0 including the branch.

In the machine cycle 5, the execution cycle control unit 4
Outputs a logic "0" signal, indicating that machine cycle 5 is the first execution cycle. In this case, the selectors 5, 6, and 7 are controlled, and the execution units 8, 9, and 10 control the execution of the control field C2F2L2 in the first execution cycle. On the other hand, at this time, although the machine cycle 5 indicates that it is the first execution cycle, the field control circuit unit 3 outputs a logic "1" signal, and the information of the control field T0 of the second execution cycle is output. Is added to the branch control unit 13 via the switch 11 as information for performing branch control. Then, in the machine cycle 5, the operation of the branch control unit 13 is performed. In this case, since the branch is not taken, the control storage address register 15 is updated to the address N2, and a read operation of the next control word from the control storage unit 1 is performed by the address data N2. In the next machine cycle 6, the execution cycle control unit 4 outputs a logical "1" signal, instructs that the machine cycle 6 is the second execution cycle, and controls the selectors 5, 6, and 7. In this case, The information of the control field of the second execution cycle is not added to the selectors 6 and 7, and only the execution unit 8 executes the control field C3. At the end of the machine cycle 6, at this time, the control storage address register 15 has already been updated to the address N2 as described above, and this address data N2
The next control word C4F4L4C5F5L5 is stored in the control storage unit 1
Although not shown, in the next machine cycles 7 and 8, the same execution control operation as in the machine cycles 3 and 4 is performed.

Next, a case where a branch is taken by execution control of a microinstruction by a control word including a branch will be described with reference to FIG. 3b.

In the machine cycles 10 and 11, a read operation from the control storage unit 1 is performed by the address data N5 of the control storage address register 15, and the read control word C6F6L6C7
Execution control of T1B0 is performed in machine cycles 12 and 13. In the machine cycle 12, the execution cycle control unit 4 outputs a logical "0" signal, and the machine cycle 12
Indicates that this is an execution cycle. In this case, the selectors 5, 6, and 7 are controlled, and the execution control of the control field C6F6L6 in the first execution cycle is performed by the execution units 8, 9, and 10. At this time, although the machine cycle 12 indicates that it is the first execution cycle, the field control circuit unit 3
Outputs a logic "1" signal, and information in the control field T1 of the second execution cycle is
It is added to the branch control unit 13 via the switch 11. And
The operation of the branch control unit 13 is performed in the machine cycle 12, and in this case, when it is determined that the branch is taken, the operation of the branch control unit 13 causes the control storage address register 15 to be stored in the control storage address register 15 via the switch 12 and the selector 14. The address data of the information from the control field (L1) of the second execution cycle is read and updated to the address B0. With this address data B0, a read operation of the next control word from the control storage unit 1 is performed. In this case, in the next machine cycle 13,
The execution cycle control unit 4 outputs a logical "1" signal to indicate that the machine cycle 6 is the second execution cycle. The execution control of the control field performed in the second execution cycle is a branch control. Since the processing has already been completed, the control field C7 of the second execution cycle is added to the execution unit 8 via the selector 5, but the execution of the control field C7 is invalidated.

At the end of the machine cycle 13, at this time, as described above, the control storage address register 15 has already been updated to the address B0 of the branch destination address, and the address data B0 causes the next control word C10F10L10C11F11L11 to be read from the control storage unit 1. The read has been performed, and in the next machine cycles 14 and 15, the same execution control operation as in the machine cycles 3 and 4 is performed.

As described above, in the microprogram control device of the present embodiment, it is possible to perform arithmetic control even when branching is performed by microinstruction execution control, and to perform branching execution control even when performing arithmetic control. Therefore, the execution efficiency in executing the microinstruction does not decrease.
Also, under the control of the field control circuit unit 3, the F1 field is used as the T field for branch control, and the L1 field is also used as the B field for branch address information, so that the width of the control word can be reduced. it can.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various changes can be made without departing from the scope of the invention.

〔The invention's effect〕

As described above, according to the present invention, when controlling the execution of a microinstruction, a decrease in the execution efficiency of the execution control of a microinstruction including a branch is minimized, and the bit width of the control storage word is reduced. Since it can be reduced, there is an effect that the system can be constructed economically.

[Brief description of the drawings]

FIG. 1 is a block diagram of a processing device by a microprogram control device according to one embodiment of the present invention. FIG. 2 is a diagram showing an example of a control word for explaining execution control of a microinstruction accompanied by branch control. 3a and 3b are time charts for explaining the execution control of a microinstruction accompanied by branch control. FIG. 4 is a conventional microprogram control method for simultaneously reading microinstructions for a plurality of execution cycles. It is a time chart explaining an example. In the figure, 1... Control storage unit, 2... Control storage data register, 3... Field control circuit unit, 4... Execution cycle control unit, 5 to 7, 14. .., 11-12... Switch, 13... Branch control unit, 15... Control storage address register, 16.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/26 320 G06F 9/28 320

Claims (2)

(57) [Claims] A control circuit for controlling an execution cycle of two machine cycles by a control word read from a control storage in one access unit, and an operation designated by information of the control word for each execution cycle of the two machine cycles A plurality of execution units for executing the control word, wherein the control word includes one field control unit, one or more control fields used in a first execution cycle, and a second control unit.
A plurality of control field parts divided into one or more control fields used in an execution cycle, and when a branch is instructed by the field control part in a control word read from the control storage, Of the control fields used in the second execution cycle, control is performed using a predetermined specific field as branch control information and branch address information in the first execution cycle. If no branch is specified, the second execution is performed. A microprogram control device comprising a field control circuit for performing control for use as a control field in a cycle. 2. The field control circuit according to claim 1, wherein, when a branch is instructed by said field control unit, and when the branch is not taken, a control field other than a specific field among control fields for a second execution cycle. 2. The microprogram control device according to claim 1, wherein control according to the following is executed in a second execution cycle.