JP3117214B2 - Sequencer microprogram control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a microprogram control method for a sequencer that controls a plurality of hardware function devices by a microprogram.

(Prior Art) FIG. 3 shows an example of the configuration of a microprogram of a sequencer of this type, which controls other hardware functional devices according to the state of the hardware functional device controlled by the microcode. It includes a sequence (condition jump 12) and a sequence (non-condition jump 13) for controlling one hardware functional device and then controlling another hardware functional device.

Conventionally, in the control of a microprogram having such a configuration, when transitioning from the program logic 11 for controlling the first hardware functional device to the program logic for controlling the next hardware functional device, conventionally, A control method has been adopted in which an address for the head is given to a control code storage device using a field in the microcode.

FIG. 4 shows an outline of a system configuration based on this conventional microprogram control method.

In FIG. 4, reference numeral 21 denotes a control code storage device for storing a microprogram for controlling a hardware function device.

A counter 22 generates an address for the control code storage device 21.

Reference numeral 23 denotes a control code latch unit that latches the microcode output from the control code storage device 21.

24 is a hardware functional device controlled by microcode.

Reference numeral 25 denotes a status permission bit decoder for performing transition control in the microcode.

26 is a microcode, 27 is a control code bus, and 28 is a control code address bus.

Here, the field of the microcode 26 used for performing the transition of the program logic as described above gives a field (Jump destination address) for indicating an address to the transition destination program logic and the address thereof to the control code storage device 21. And a field (status permission bit) for controlling the operation.

As described above, according to the conventional method using the microcode 26 that performs only the transition operation when performing the logic transition between the program logics controlling the hardware functional device 24, 24 control processing will be interrupted by the processing of the microcode 26 for the transition control between program logics,
As a result, there was a problem that the processing speed of the hardware functional device 24 was reduced.

Conventionally, a system as shown in FIG. 5 has been proposed to solve this problem.

That is, in this conventional method, the microcode
26a is provided with both a field for controlling the hardware function device 24 and a field for performing transition of the program logic (decoders 25a and 25b are also provided corresponding to these fields). In this case, the speed is increased by simultaneously and continuously performing the above control processing operations.

However, in the case of this conventional method, the microcode
The length of the control code storage device 21 for storing the microcode 26a is inevitably increased.

(Problems to be Solved by the Invention) As described above, in the conventional microprogram control method of the sequencer, when a transition between program logics for controlling the hardware function device is performed, the execution of the logic transition and the transition destination are performed. When an instruction is given by microcode, there is a problem in that the logic transition control is performed while other controls are interrupted, thereby reducing the control processing speed of the hardware functional device.

In addition, if both a field for instructing a logic transition to the microcode and a field for controlling the hardware functional device are provided to improve the control processing speed, the microcode length becomes long, and the control code storage device for storing the microcode becomes large. There was a problem of becoming.

The present invention eliminates this problem, and can continuously increase the speed of processing by continuously controlling hardware functional devices even during logic transition control, and by shortening the microcode length used for the control. It is an object of the present invention to provide a microprogram control method for a sequencer that can prevent an increase in the size of a control code storage device.

[Configuration of the invention]

(Means for Solving the Problems) The present invention is directed to a microprogram in which program logics for individual control of a plurality of hardware function devices are grouped together as a series of control information and stored in a control code storage device. A plurality of address registers for providing a transition address required for transition control of the program logic to the control code storage device, and a transition to a head of the program logic at an initial operation of the sequencer. Loading means for loading an address into a corresponding address register, and when transitioning to another program logic, the address register loaded with a transition address required for the control is changed before the transition output from the control code storage device. Program Output means for selecting based on the program logic set in the final microcode of the logic and the status display signal of the hardware function device, and outputting the transition address in the selected address register to the control code storage device. It is characterized by having.

(Operation) In the present invention, an address necessary for performing a transition of program logic is provided to the control code storage device by a register without using microcode.

At this time, first, an address for the head of the program logic is loaded into the register by the initial operation of the microprogram.

Then, in the program logic that actually performs the control operation of the hardware functional device, when the processing in the logic is completed and the transition to the next logic is performed, the logic transition included in the final microcode of the logic is performed. The control field to be performed is used to instruct a transition operation, determine the status display signal of the hardware functional device, and select a register.

For this reason, even in the logic transition control, it is not necessary to interrupt the control processing operation of a series of hardware functional devices,
High-speed processing can be realized.

In addition, since the microcode field is not used to indicate the address value for the program logic, the microcode length can be reduced, and the size of the device for storing the microcode can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an outline of a system configuration according to a microprogram control method of a sequencer of the present invention.

In the method of the present invention, an address register 29 is provided to give an address necessary for performing a transition of the program logic.

The field of the microcode 26A is composed of a field for controlling the hardware functional device (hardware control bit) and a field for performing transition of the program logic (status permission bit).

To decode each field of the microcode 26A, decoders 25A and 25B are provided corresponding to each field.

Otherwise, the configuration is the same as that of the conventional system. A control code storage device 21 for storing a microprogram, a counter 22 for generating an address for the control code storage device 21, and a microcode output from the control code storage device A control code latch unit 23 for latching the code 26A and a hardware function device 24 controlled by the microcode 26A are provided.

The operation of the microprogram control method will be described below.

First, a microprogram for controlling the hardware function device 24 is stored in the control code storage device 21.

The counter 22 supplies an address for executing a certain program logic to the control code storage device 21 through the control code address bus 28 in accordance with the operation cycle of the hardware function device 24.

The control code storage device 21 outputs the previously stored microcode 26A to the control code latch unit 23 through the control code bus 27 according to the given address value.

Microcode latched by control code latch unit 23
26A is decoded by decoders 25A and 25B provided for each field of the microcode 26A, and is used for function control of each.

In a normal control process of the hardware function device 24, the status permission bit in the microcode 26A is not set, and only the hardware function device 24 is controlled by setting only the hardware control bit.

On the other hand, a microprogram that controls a plurality of hardware function devices 24 and performs one completed process is configured using a plurality of program logics that control one hardware function device 24. When performing transitions between program logics, use microcode
The status permission bit of 26A is set, and the status display signal of the hardware functional device 24 is transmitted to the counter 22 and the address register 29 to select and set the address of the transition destination program logic.

Since the microcode 26A has the status permission bit for performing the state transition and the control bit for controlling the hardware function device 24, the control operation of the hardware function device 24 is interrupted even when the transition operation is instructed. You don't have to.

In addition, since the address for the transition operation is set from the address register 29, a field for designating the address can be deleted from the microcode, thereby shortening the microcode length.

Next, FIG. 2 shows a specific configuration example of a system to which the microprogram control method is applied.

2, reference numeral 30 denotes a sequencer according to the method of the present invention shown in FIG. 1, and reference numeral 31 denotes a control code storage device in which a microprogram is stored.

Reference numeral 32 denotes a hardware function device controlled by a microprogram. In this example, there are a plurality of units A to F.

33 is a FIFO (first-i
n is a first-out (first-in-first-out) circuit, and 35 is a data bus for multiplexing the data of the terminal 34 and the parameters of the hardware functional units 32A to 32F.

The hardware in FIG. 2 is a hardware functional device 32A.
ＦF and the data of the terminal 34 are multiplexed on the data bus 35, and the operation of outputting the multiplexed data to the transmission line is performed.

The sequencer 30 has program logic for controlling each of the hardware function devices 32A to 32F, and selects a parameter corresponding to the multiplexing speed according to the value of the status display signal of each of the hardware function devices 32A to 32F.

Considering the case where the parameters of the hardware function device 32A are multiplexed and then the parameters of the hardware function device 32B are multiplexed, in the microprogram control method of the sequencer 30 according to the present invention, the control of the hardware function device 32 and The transition operation of the program logic can be performed simultaneously.

Therefore, by setting the status permission bit in the final microcode of the program logic for multiplexing the parameters of the hardware functional device 32A, the multiplexing of the final parameters of the hardware functional device 32A and the next hardware functional device 32B And the setting of the start address of the program logic for controlling the multiplexing can be performed simultaneously, thereby improving the multiplexing speed.

As described above, when the multiplex speed is improved, the allowable speed of the terminal speed supported by the multiplex speed can be naturally improved.

Further, in the present invention, the address given to the control code storage device 31 is given not from the microcode but from a register set in advance, and the microcode length is shortened, so that the hardware excluding the sequencer 30 and the terminal 34 is used. When the functional devices 32A to 32F are manufactured as a gate array, the number of pins of the gate array can be reduced.

〔The invention's effect〕

As described above, according to the present invention, a plurality of address registers are provided, and at the initial stage of operation of the sequencer, a transition address for the beginning of the program logic is loaded for each corresponding address register, and the transition to another program logic is performed. When processing is performed, the program logic set in the final microcode of the program logic before the transition and the status display signal of the hardware functional device are used as indices (that is, while the processing operation of the hardware functional device is performed). Since the corresponding transition address is provided from the address register to the control code storage device, there is no need to interrupt other control, for example, operation control of a destination hardware function device external to the sequencer, in transition control of the program logic. Program logic transition (ja Up instruction) speed can be of a series of sequence processing, including.

Further, in the present invention, when performing a process of transiting to another program logic, a transition address is provided from the address register. Therefore, a field for designating the transition address is provided in the microcode output from the control code storage device. There is no need, and the microcode length can be shortened accordingly, and the shape of the device for storing the microcode can be downsized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a system configuration according to a microprogram control method of a sequencer according to the present invention, FIG. 2 is a configuration diagram of a system applying the microprogram control method of a sequencer according to the present invention, and FIG. Is a conceptual diagram showing the general structure of a sequencer microprogram.
FIG. 1 is a diagram showing an example of a system configuration according to a conventional microprogram control system, and FIG. 5 is a diagram showing another example of the configuration of this type of conventional system. 11: Program logic, 12: Condition jump, 13: Non-condition jump, 21: Control code storage device, 22: Counter, 23: Control code latch unit, 24: Hardware function device, 25A ... Decoder for status permission bit code, 25B ... Decoder for control code, 26A ... Microcode, 27 ... Control code bus, 28 ... Control code address bus, 29 ... Address register, 30 ... Sequencer, 31 ... Control code storage devices, 32A to F ... Various hardware function devices, 33 ...
... FIFO (first-in first-out) circuit, 34 ... Terminal, 35
.... Parameters and FIF of hardware functional units 32A to 32F
Data bus for multiplexing O33 data

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Akira Watanabe 3-1-1 Asahigaoka, Hino-shi, Tokyo Toshiba Communication Systems Engineering Co., Ltd. (56) References JP-A-61-58042 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) G06F 9/26 320

Claims (2)

(57) [Claims] 1. A microprogram control method for a sequencer which targets a microprogram stored in a control code storage device by integrating program logic for individual control of a plurality of hardware function devices as a series of control information having a meaning. A plurality of address registers for providing a transition address necessary for the transition control of the program logic to the control code storage device; and, at an initial stage of the operation of the sequencer, loading a transition address for the top of the program logic into a corresponding address register. The loading means and, when transiting to another program logic, an address register loaded with a transition address required for the control is stored in the control code storage device. Output means for selecting a transition address in the selected address register to the control code storage device, based on the program logic set in the device and the status display signal of the hardware function device. The sequencer's microprogram control method. 2. A method according to claim 1, wherein both a signal for controlling the transition of the program logic and a signal for controlling the operation of the hardware functional device are set in the state display signal, and the transition of the program logic controls the transition from the address register appropriately. 3. The method according to claim 1, wherein a process of selecting a proper transition address and providing the selected control address to the control code storage device and a control process of the hardware functional device are enabled in parallel.
Microprogram control method of the described sequencer.