JPS6361331A - Control device for computer - Google Patents

Abstract

PURPOSE:To accelerate a processing speed by replacing the processing contents of a computer shown by plural instruction code groups with one new instruction code and decreasing the number of times to read an instruction code from a main memory. CONSTITUTION:When an instruction code 1 to execute a microprogram is sent from a main memory 3 to a control part 6, the code is decoded by a microprogram sequencer 4 and the processing procedure is sent to a RAM 10 for accommodating the microprogram. From a RAM 10, in accordance with the processing procedure from the sequencer 4, the same signals as the signals outputted from a ROM 5 for accommodating a microprogram, such as the output instruction of a signal for an arithmetic control to an arithmetic logical part 7, a signal to select a register to a register group 8, a data latch signal to the register, and the signal such as a memory reading and a memory writing to a bus control logical circuit 9 are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Sedentary Work Application] The present invention relates to a control device for improving the processing speed of a computer, for example.

[Conventional technology]

FIG. 2 is a diagram showing an example of a conventional computer control device. In FIG. 1, (1) is an instruction code for controlling the execution procedure of the computer, and (2) is an instruction code fi.
(3) is the main memory for storing program (2).

(4) is a microprogram sequencer that instructs the instruction code + 11 decoder J [instruction code sent out sequentially from the main memory (3), and (5) is a microprogram sequencer (a control for controlling the execution procedure of the computer according to instructions in ROMI for storing microprograms that create signals,
(read-only memory), (61 is a control unit consisting of a ROM +51 for storing microprograms and a microprogram sequencer (41), (7) is an arithmetic logic unit that performs arithmetic operations according to instructions from the control unit (61), (8) (9) is a group of registers that holds data input to the arithmetic logic section (7), arithmetic results, etc., and (9) is a bus control logic circuit that controls the main memory IJ (31%) according to instructions from the control section (6).

The next lζ operation will be explained.

In the initial state of the computer, the microprogram address output from the i microprogram sequence "j (41) and the value of the register group (8) (set to 1G).

When the computer starts up, the microprogram sequencer (4) transfers data from the microprogram storage ROM+51.
On the other hand, microprogram addresses are sent out sequentially starting from address 0. From the microprogram storage ROM+51, a control signal corresponding to the microprogram address is sent to the register group (81, arithmetic logic section (7), and bus control circuit (9).The control signal sent here is Performs the following controls.

First, the register group (8) is caused to send memory address 0 to the main memory (3). Next, the bus control logic circuit (9) is caused to send a memory read signal to the main memory (3). These signals send the instruction code (1) stored at address 0 of the main memory (3) to the microprogram sequencer (4) and the register group (8). In this way, the first instruction code is etched seven times.

The fetched instruction code is decoded by the microprogram sequencer (41) and stored in the microprogram storage ROM+51 according to the controller corresponding to the instruction code.
by sequentially specifying the addresses of .

Microprogram storage ROM +51 to register group (8), arithmetic logic section (7) and bus control logic circuit (9)
) etc. are sequentially sent out. Based on this control signal, the following control is performed. Data is output from a specific register in the register group (8) to the arithmetic logic unit (7). The arithmetic logic section (7) performs various arithmetic operations and logical operations based on this data, and stores the results of these operations in specific registers of the register group (8). Also, address information in a specific register of the register group (81) is sent to the main memory (3).

Data is transferred between the previously specified address of the main memory (3) and the register group (81) in synchronization with the memory read signal or memory write signal output from the bus control logic circuit (9).

In this way, the computer fetches instructions.

The instruction code is
The processing content is uniquely defined in advance, and the computer performs various calculations and controls according to this definition.

[Problem that the invention seeks to solve]

Conventional computer control devices only operate in accordance with predetermined instruction codes.

Since multiple instruction codes are combined in order to perform a single process, it is necessary to read the instruction codes from main memory multiple times, and the processing speed decreases due to the time required for reading. There was a point.

This invention was made to solve the above-mentioned problems, and it is a computer control system that can increase processing speed by defining instruction codes that perform specific processing depending on the processing content. This is what we provide.

[Means for solving problems]

The computer control device according to the present invention has a microprogram storage RAM (Random Access Memory) added to the control unit that can be written by a user's program, so that any microprogram can be registered by the user's program. The rest is one Goikuro instruction that can be executed by defining one instruction code.

[Effect]

The computer control device in this invention is:

Processing speed can be increased by replacing the computer processing content indicated by a certain group of instruction codes with a new instruction code and reducing the number of times instruction codes are read from the main memory.

〔Example〕

FIG. i is a diagram illustrating a -5ii embodiment of the present invention.

αI can be programmed by the program (2), and after V programming, the microprogram outputs the same control signal as the microprogram storage ROM to the bus control logic circuit (9) etc. according to instructions from the microprogram sequencer (4). RAM for program storage, αυ is an address register that temporarily holds the address read into RAMH for storing microprograms, α2 receives data sent from main memory (3) or register group (8), and stores microprograms. Data bus buffer (L
Reference numeral 3 designates a selector which selects whether addressing of the microphone 4 program storage RAMQ (I) is to be performed by the microprogram sequencer (4) or by the address register I in response to an instruction from the microprogram storage ROM +51.

The computer control device in this invention is:

This allows the user to define new instructions as micro-instructions using a program, and can be implemented with the configuration described above. First, selector α from main memory (3)
An instruction for selecting 3 is fetched. Then, the microprogram sequencer (4) decodes the instruction and stores it in the microprogram storage ROM! 51 instructing the processing procedure, microprogram storage ROM +5
1 instructs selector 0 to select the address register (11) side. Next, program (2) sets the address of the microprogram storage RAM (Lf3) in the address register αυ. Next, program (2) transfers the microprogram to the microprogram via data bus buffer a3%. The program is sent to the RAM αG for storing the program, and written to the address specified by the address register I. In this way, by repeating the setting of the address register αυ and writing the microprogram, the microprogram that performs the desired process is written to the RAM αG for storing the microprogram. Next, the program (2) switches the selector αj so that the microprogram sequencer (4) can specify the address of the RAMQ port for storing the microprogram.

The instruction hood (1) that has been introduced into the microprogram as described above is stored from the main memory (3).
Once sent to the microprogram sequencer (411), it is decoded and the processing procedure is sent to the microprogram storage RAM Qα.From the microprogram storage RAM αe, the microprogram sequencer (411) etc. According to the processing procedure, a signal for arithmetic control is sent to the arithmetic logic unit (7), a register selection signal and a data latch signal to the register are sent to the register group (8), and a bus control logic circuit (9) is sent. Signals similar to those output from the microprogram storage ROM, such as output instructions for signals such as memory read and memory write, are output.

In this way, once a microprogram is defined as a single microinstruction by a user, it can be executed as many times as it is mixed with existing instruction codes.

Incidentally, in the above embodiment, an example was shown in which RAM was used for storing a microprogram, but the same effects as in the above embodiment can be obtained if the memory element is capable of writing and reading.

〔Effect of the invention〕

As explained above, in this invention, any microprogram can be set and executed by a program, so the processing speed can be improved by creating instructions according to the processing contents by the user or himself. can. Also.

If the microprogram storage ROM is damaged, the same functionality can be obtained by storing a microprogram equivalent to the damaged microprogram in the microprogram storage memory.

[Brief explanation of the drawing]

Figure 1 shows a computer system (
FIG. 2 is a diagram showing a conventional computer control device. In the figure, (1) is an instruction code, and (2) is a program. (3) C main memory, (4) micro program sequencer, (51 ROM for storing micro programs, (6
1 is a control unit, (7) is an arithmetic logic unit, (8) is a group of registers, (9) is a bus control logic circuit, αG is a RAM for storing a microprogram, αIt is an address register, (1z is a data bus spanner, 13 is a selector. In FIG. 1, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A main memory that stores a program consisting of a group of instruction codes, a microprogram sequencer that instructs the decoding procedure of the program in this main memory, and a microprogram sequencer that decodes the program according to the instructions of the microprogram sequencer and executes the computer's execution procedure. A ROM for storing a microprogram that outputs control signals for control, an arithmetic logic section that performs arithmetic operations and logical operations based on the control signals, and data instructed by the program and arithmetic data output from the arithmetic logic section. A computer control device comprising a group of registers for holding, and a bus control circuit that controls reading from and writing to the main memory based on the control signal, the microprogram sequencer and the ROM for storing the microprogram. A control unit consisting of a writable microprogram storage memory, an address register that temporarily holds a write address to this microprogram storage memory,
The data bus buffer that receives data sent from the main memory and register group and sends it to the microprogram storage memory and the address specification of the microprogram storage memory are performed by the microprogram sequencer, or A control device for a computer, comprising: a selector for selecting whether to use the address register based on the control signal.