JPH02110631A - Microprogram controlling method - Google Patents

Abstract

PURPOSE:To apply a microprogram to the complicated instruction system of the instruction code of two or more words as well by dividing a microprogram storage device into pages consisting of plural words, and providing a controllable page assignment register and an address assignment register to fetch the contents of an instruction register. CONSTITUTION:The contents of the instruction register 11 is stored in the address assignment register 14 through an address selection circuit 13. The contents of the page assignment register 51 and the address assignment register 14 are coupled, and one word of a microinstruction is read out from the microprogram storage device 15. The operation controlling part of the read microinstruction is stored in a microinstruction register 16, and a page controlling part and an address controlling part are returned to the page assignment register 51 and the address selection circuit 13 respectively. The contents of the register 16 are made into various kinds of control signals through a microinstruction decoder 17. Thus, by executing successively a series of the microinstructions, the microprogram can be applied to the complicated instruction system of the instruction code of two or more words.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control method having a microprogram storage device having an instruction decoding function.

[Conventional technology]

FIG. 1 shows the configuration of a conventionally commonly used microprogram control device, which commands raster 11. Instruction decoder]-2, address selection circuit 13. Microprogram address register 14, microprogram storage device 15. It consists of a microinstruction register 16 and a microinstruction decoder 17. In the instruction reading microroutine, one instruction word is read from the main memory and stored in the instruction register 11. The instruction decoder 12 decodes the contents of the instruction register 11 and generates the initial address of the microroutine corresponding to the instruction code. The initial address generated by instruction decoder 12 is stored in microprogram address register 14 via address selection circuit 13, and one word of the microinstruction corresponding to that address is read from microprogram storage 15. The arithmetic control section (code) of the read microinstruction is stored in the microinstruction register 16, and the address control section (code) of the microinstruction is stored in the address selection circuit 13.
will be returned to. The contents of the microinstruction register 16 are decoded by a microinstruction decoder 17 to generate various control signals.

On the other hand, the contents of the address control section returned to the address selection circuit 13 are transferred to the microprogram address register 14, and the microinstructions are sequentially read out and executed.

In the microprogram control method, all control contents are stored in the microprogram storage device, so different processing can be performed simply by rewriting the contents of the storage device, but in the method shown in Figure 1, processing for different command systems is possible. In order to realize this, it is also necessary to change the contents of the instruction decoder 17. However, since the instruction decoder usually has a configuration that depends on the instruction system, in order to realize a completely different instruction system, a sufficiently large decoding circuit must be prepared or a troublesome change in the circuit configuration must be made. That is, in the system shown in FIG. 1, the configuration of the instruction decoder has become a major problem that affects the versatility of the microprogram control device.

FIG. 2 shows a timing chart of the microprogram control device having the configuration shown in FIG.
1, the output 1b of the instruction decoder 12, the output Lc of the microprogram address register 14, the output 1d of the microprogram storage 15, and the output 1e of the microinstruction register 16 are shown juxtaposed with the basic clock. . In the figure, the shaded area indicates a period in which the signal is not determined due to the delay time of the circuit. instruction register 1
After the output 1a of the instruction decoder 12 is determined, the output 1a of the instruction decoder 12 is
The time it takes to determine b, in other words, the time it takes to decode an instruction and generate an initial address, varies depending on the configuration and size of the instruction decoder, but is roughly comparable to the time required to access the storage device. FIG. 2 shows that one microcycle of waiting time is required before reading from the microprogram storage device begins. Therefore, in the system shown in FIG. 1, the configuration of the instruction decoder poses a problem that greatly affects the high speed performance of the processing device.

FIG. 3 shows what is known as the mapping method, which is used in computers with instruction systems. This method has a fixed bit-bang generation circuit 31, and uses the concatenation of the output of the bit-bang generation circuit 3 and the contents of the instruction register 11 as the initial address of the microroutine. It is a method. FIG. 4 shows a timing chart for the method shown in FIG. 3, and shows the relationship between the output 3a of the instruction register 11 and the output 3b of the microprogram address register 14. The feature of this method is that since no instruction decoder is used, the time required to generate the initial address of the microroutine can be shortened.As shown in FIG. 4, after the output 3a of the instruction register 11 is determined, the microprogram address register The time it takes for the output 3b of 4 to be determined is 1 microcycle shorter than in the method shown in FIG.

However, in this mapping method, the branch destination for the instruction code is fixed, so it cannot be used for a complex instruction system where the instruction code is two or more words, and is not a general method. Also, even when multiple instruction codes include common processing, the branch destinations are different, so MicroProgera! 1. This is not a practical method because the capacity of the storage device increases.

[Problem to be solved by the invention]

A conventional microprogram control system using an instruction decoder has a problem in that processing speed is slow because it requires time to decode an instruction and generate an initial address. Furthermore, since an instruction decoder is provided between the instruction register and the microprogram storage device, the control structure becomes complicated. In particular, in order to process a complex instruction system in which the instruction code is two or more words, the instruction decoder must also have a sufficiently large size and a complicated structure.

On the other hand, the mapping method of the prior art does not use an instruction decoder and can achieve high speed, but there is a problem that it cannot be applied to a complicated instruction system where the instruction code is two or more words.

SUMMARY OF THE INVENTION An object of the present invention is to realize a microprogram control method that is fast, flexible, and versatile and can be applied even to complex instruction systems in which the instruction code consists of two or more words.

[Means to solve the problem]

In order to achieve the above object, the present invention divides a microprogram storage device into pages consisting of multiple words, and has a page specification register that can be controlled by the microprogram, and a page specification register that can directly capture the contents of an instruction register. It has an addressing register and allows multiple pages to be used as instruction decoding areas.

[Effect]

After taking the first word of the instruction code into the addressing register and branching to the first decode page, if the first instruction word is a specific code that defines an extended instruction, the second word of the following instruction code is read out, the second decode page is specified, the second word of the instruction code is loaded into the address designation register, and the decode branch is executed again.

〔Example〕

FIG. 5 shows the configuration of a microprogram control device according to an embodiment of the present invention, in which an instruction register 11. Address selection circuit 13. Addressing register 14. Page specification register 51. A microprogram storage device 15° consists of a microinstruction register 16 and a microinstruction decoder 17. Here, the page register 51 is related to the present invention. The contents of the instruction register 11 read from the main memory (not shown) are stored in the address designation register 14 via the address selection circuit 13 in response to a control signal (not shown).

The contents of page designation register 51 are controlled by a microprogram. A concatenation of the contents of the page designation register 51 and the address designation register 14 is used to designate the address of the microprogram storage device,
One of the microinstructions from the microprogram storage device 15
Read out the word.

The arithmetic control section of the read microinstruction is stored in the microinstruction register 16, the page control section is stored in the page designation register 51, and the address control section is stored in the address selection circuit 13.
will be returned to. The contents of the microinstruction register 16 are decoded by a microinstruction decoder 17 to provide various control signals. The contents of the instruction register 11 are not selected by a control signal (not shown), but the address control part of the microinstruction returned to the address selection circuit 13 is selected and stored in the address specification register 14, and the contents of the page specification register 51 and the address are selected. A concatenation of the contents of the designated register 14 is used to read a microinstruction from the microprogram storage device. In this way, a series of microinstructions are executed sequentially. The address space of the microprogram storage device 15 is classified into page areas in which a page control unit consisting of a plurality of bits is a unit of a microinstruction having a common plurality of words. A certain page area of the microprogram storage device 15 is allocated as an area for storing the first microinstruction of each microroutine branched according to the contents of the instruction register 11, and arbitrary branching is possible. Furthermore, by controlling the contents of the page designation register 51, a plurality of branching methods are possible for the same instruction code, and a complex instruction system can be handled. Furthermore, since no instruction decoder is provided, it is possible to accommodate different instruction systems by simply changing the contents of the microprogram storage device 15, thus maintaining sufficient versatility.

Furthermore, it is also applicable to complex extended instructions where the instruction code is two or more words.

FIG. 6 shows a timing chart for the method shown in FIG. 5, and the output 5a of the instruction register 11 and the outputs 5b of the page designation register 51 and address designation register 14 are also shown as a basic clock. In the method of the present invention, an instruction decoder is not placed immediately after the instruction register 11,
Directly address the contents of instruction register 11 to register 1
4, the time required to generate the initial address of the microroutine can be shortened, similar to the conventional mapping method shown in FIG. FIG. 6 shows that the timing structure of this method is similar to the conventional mapping method shown in FIG. An example of a specific processing procedure using the processing method shown in FIG. 5 will be explained. First, regarding the instruction system being considered, the instruction code is expressed in 8 bits, the upper 3 bits specify the addressing mode, and the lower 5 bits specify the content of the execution process. Each instruction is roughly divided into the following two types depending on the difference in processing procedure.

(A) Is the operand to be processed a register?
Alternatively, instructions that do not require operands include accumulator manipulation instructions and subroutine return instructions. An instruction whose upper three bits are OOo is an instruction of this type, and after the instruction reading routine is completed, the instruction is directly branched to a processing routine corresponding to each instruction code and processed.

(B) Those that use memory as an operand include load instructions from memory to an accumulator, operation instructions between the accumulator and memory, and jump instructions. In this type of instruction, the upper 3 bits of the instruction code are 001 to 111, the upper 3 bits specify the calculation mode of the operand address, and the lower 5 bits specify the content of the execution process. Addressing modes include direct addressing, indirect addressing, and relative addressing. In this type of instruction, after the instruction reading routine ends, the program branches to each address calculation routine, and after the address calculation ends, it branches to the execution routine corresponding to each instruction.

In order to process the above instruction, the instruction register 11 in FIG.
．． Addressing register 14. Page specification register 51
Each is 8 bits.

8 bits and 2 bits are used, and each address page of the microprogram storage device 15 is assigned the following functions.

(1) (00), (01) Pages are used as work areas, and the second and subsequent words of the instruction reading routine and each processing routine are stored.

(2) (10) Allocated as the first decoding area of the page instruction code, the first word of each routine of type (A) instructions and the first word of each address calculation routine of type (B) instructions are Stored.

(3) (11) The first word of each execution processing routine is stored in the second decode area of the page (B) type instruction. In the instruction reading microroutine, one word of the instruction is read from the main memory and stored in the instruction register 11. When the read routine is completed, (10) is set in the page designation register 51, the contents of the instruction register 11 are set in the address designation register 14, and the program branches to the address corresponding to the instruction code of the (10) page. In the case of an (A) type instruction, the microroutine starting from the corresponding address of the (10) page is an execution processing routine corresponding to each instruction, and returns to the instruction reading routine after completing each execution processing. (B)
In the case of a type instruction (10), the address calculation routine starts from the corresponding address of the page. When the address calculation routine is finished, (11) is stored in the page designation register 51 and the instruction register 11 is stored in the address designation register 14 again.
The same contents of are set, and a branch is made to the corresponding address of the page (11) specified by the page designation register 51. (11) Each routine whose first word is page is an execution processing routine for each command, and when the execution processing is finished, the routine returns to the command reading routine. here.

(B) Address calculation and execution processing of type instructions are common to multiple instruction codes, so when branching to pages (10) and (11), microinstructions at multiple addresses (instruction codes) are It becomes the content. In the system of this embodiment, in such a case, one word of the microprogram storage device 15 is allocated to multiple addresses (instruction codes) where the microinstruction is the same, and the actual microprogram storage device is The aim is to reduce the capacity of 15. FIG. 7 is provided to explain this and shows the configuration of the microprogram storage device 15. In the figure, the x mark indicates a portion that is not decoded. The microprogram storage device 15 includes an AND circuit 71 that decodes an address input and outputs a signal indicating one word of the storage device;
It consists of an OR circuit 72 which is driven by the output of the circuit 71 and outputs the contents of one word of the memory device. In this embodiment, the instruction code is input as is as the address. Conventionally, the AND circuit 71 of a conventional memory device completely decodes an address input and assigns one word of the memory device to one address (instruction code), but in the method of the present invention, the AND circuit 71 An effective method is to perform partial address decoding depending on the situation. That is,
When branching to each addressing routine of (lO) page with a ([3) type instruction, the page specification part of the upper 2 bits of the address (instruction code) and the following 3 bits are decoded, and the lower 5 bits of the address (instruction code) are decoded. The configuration is such that the bits are not decoded, and the lower 5 bits are different, but the page specification part of the upper 2 bits of the address (instruction code) and the following upper 3 bits from the instruction register 11 are common. ), and (11) In the page, only the upper 2 bits of the (instruction code) of the address and the lower 5 bits are decoded, and the instruction register 1 is decoded.
The AND circuit 71 may be configured so that the upper three bits from 1 are not decoded. Such a method becomes more effective when the contents of the address decoder and the contents of the storage device are simultaneously designed, especially when a read-only memory is used as the microprogram storage device.

In addition, in the explanation of FIG. 7 etc., type (A) instructions are used.

(B) Although only an example of a one-word instruction code such as a type instruction is described, the present invention can also be applied to an instruction such as an extended instruction whose instruction code spans two words. In other words, after taking the first word of the instruction code into the address specification register 14 and branching to the first decode page, reading the second word of the following instruction code, specifying the second decode page, and branching again to decode. You can configure it like this.

FIG. 8 shows another embodiment of the present invention, which differs from FIG. 5 in that it includes an auxiliary page designation register 81, an auxiliary command register 82, and a page selection circuit 83.
Furthermore, it has a configuration that can efficiently process complex command systems. Each component and its function is listed below.

(1) Auxiliary page register 81 4 bits. Holds data to be set in the page designation register 51. Any content can be set in advance using a microprogram.

(2) Instruction register 11 8 bits. Holds one word of the instruction read from main memory.

(3) Auxiliary instruction register 82 8 bits. It has the same function as the instruction register 11. By having two instruction registers, it has a structure that can accommodate complex instruction systems.

This register has an additional function that allows arbitrary bits to be set or reset by microinstructions. This effect will be explained later.

(4) Page selection circuit 83 This circuit selects whether the data to be set in the page specification register 51 is the contents of the auxiliary page specification register or the page control part of the microinstruction read from the storage device. It operates with a selection signal from.

(5) Address selection circuit 13 The data to be set in the address register is selected from (i) the output of the instruction register 11, (ii) the output of the auxiliary instruction register,
(iii) A circuit that selects the microinstruction address control unit, and operates in response to a control signal from the microinstruction.

(6) Page register 51 4 bits. It manages the upper 4 bits of the 12-bit address of the microprogram storage device.

(7) Address register 14 8 bits. Manages the lower 8 bits of the storage device address.

(8) AND circuit 71 12 bits x (number of memory words). Decodes the address to point to a word in storage. Address space is the top 4 addresses
Bits are classified by common areas (pages). Address decoding attempts to reduce the number of storage words by performing partial decoding as much as possible.

(9) OR circuit 72 (number of memory words) x 32 bits. Stores microprograms. It is read-only memory.

(10) Microinstruction register 16 Holds the arithmetic control section of microinstructions read from the microprogram storage device.

(11) Microdecoder 17 Decodes the contents of the microinstruction register 16 and generates control signals necessary for other arithmetic circuits and gate circuits.

Next, the target instruction system will be explained. Instructions are roughly divided into the following five types based on their processing methods.

(A) Direct branching to the execution routine corresponding to the instruction code.

(8) After calculating the operand address, branch to the corresponding execution routine. There are multiple types of addressing modes, and the next word following the instruction code defines the addressing mode.

(C) When the instruction code of the first word is a certain value,
Furthermore, the second word following the first word specifies a new instruction and branches to the execution routine corresponding to that instruction.

(D) Cases of type (C) that require calculation of operand addresses. Here, the addressing mode is (B
) is the same as the type of

(E) Each bit of the second word following the instruction code is a permission flag for the corresponding process.

FIG. 9 illustrates the flow of processing for the above five types of commands. In order to execute the above instructions, the following functions are assigned to the address space of the microprogram storage device.

(1) (0000), (0001) Pages are used as work areas.

(2) (0010) page Decode area for the first word of the instruction code.

(3) (0011) A decode area for branching to an execution routine after address calculation in a page (B) type instruction.

(4) (0100) Decode area of the second instruction code of page (C) and (D) type instructions.

(5) (0101) A decode area for branching to an execution routine after address calculation in a page (D) type instruction.

(6) (0110) page (E) Decode area for execution routine of type instructions.

(7) (0111) page Decode area for address calculation.

Pages (1000) to (1111) are undefined reserve areas and are not used in the above instruction system.

Next, the flow of processing will be explained using FIGS. 8 and 9.

In the instruction reading microroutine, one word of the instruction is read from the main memory and stored in the instruction register 11. When the read routine is finished, the page register 51 contains (
0010), the contents of the instruction register 11 are set in the address designation register 14, and the program branches to one of the (0010) pages. (A) For type instructions, (ooto)
The page is the start area of the execution routine, and (00
10) The first word microinstruction of the execution routine is stored at the corresponding address of the page. Microinstructions following the second word of each routine are stored in the work area.

For type (B) instructions, address calculation is performed prior to the execution routine. Here, the address calculation routine is (B
) type and (D) type instructions, but the branch destination after address calculation is different. The auxiliary page designation register 81 is used as a means to efficiently process this. Further, the address calculation process differs depending on the content of the next word following the instruction code, but the content of the instruction register 11 must be saved because it includes information for branching to the next execution routine. Therefore, the auxiliary instruction register 82 is used for address calculation. therefore.

(0010) The processing of the type (B) instruction in the page reads the next word following the instruction code from the main memory, sets it in the auxiliary instruction register 82, and sets the branch destination page after address calculation in the auxiliary page designation register 81. (0011). After that, set the contents of the auxiliary instruction register to the address register.0111. ) Branches to the address calculation routine corresponding to each addressing mode of the page. When the address calculation routine is finished, the contents of the auxiliary page designation register 81 are set to the page register 51, and the contents of the instruction register 11 are set to the address register 14. As a result, in the (B) type instruction, the (0011) page is set to (
D) type instructions branch to each execution routine of the (0101,) page.

(C) type and (D) type instructions need to branch by the second instruction code, so on page (0010),
When it is decoded that it is a C) type or (D) type instruction, the processing here is to read the second word following the instruction code from the main memory and set it in the instruction register 11. Thereafter, the contents of the instruction register 11 are set in the address designation register 14 (0100), and the process branches to the page. (
In the case of C) type instructions, the (0100) page is the top area of each execution routine. In the case of a type (D) instruction, the next word is read from the main memory and set in the auxiliary instruction register 82, and the branch destination page (0101) after address calculation is set in the auxiliary page specification register 81. Thereafter, the contents of the auxiliary instruction register 82 are set in the address designation register 14, and the program branches to a page address calculation routine (0111). (E) type instructions can be processed by using a conditional jump of a microinstruction for each bit of the second word following the instruction code, but this method has the disadvantage that the microroutine becomes longer and the processing speed becomes slower. As a solution to this problem, the auxiliary instruction register 82
Uses bit-by-bit set and reset functions. (00
10) Processing of a type (B) instruction in a page is to read the second word following the instruction code from the main memory and set it in the auxiliary instruction register 82. Thereafter, the contents of the auxiliary instruction register 82 are set in the address designation register 14 (0110), and the process branches to the page. (0110) The page is decoded bit by bit with priority given to each bit as shown in FIG. 10, and branched to an execution routine corresponding to each bit. If all bits are It_O11, the process is to do nothing and return to the instruction read routine. The execution routine corresponding to each bit resets the corresponding bit of the auxiliary instruction register 82 after performing the process corresponding to that bit. Then again,
The contents of the auxiliary instruction register 82 are set in the address register 14 (0110), and the process branches to the page. By configuring the microprogram in this way, it will continue until all bits of the auxiliary instruction register 82 become "0", that is, 4
11 Bits are processed in order starting from the highest priority bit until all processing corresponding to the IT bit is completed. Therefore, as a result of using the present invention even for special instructions such as type (E) instructions, the number of memory words can be reduced and processing can be performed at high speed.

According to the embodiment illustrated above, a high speed ratio can be achieved by setting the contents of the instruction register directly to the address specification register without going through the instruction decoder, and it has a page specification register that can be controlled by microinstructions. It can also handle complex instruction systems, and has flexible versatility because the instruction decoding function is concentrated in the storage device.

In addition, because the address decoder of the storage device does not perform complete decoding, one address decoder of the storage device may
Since words can be made to correspond, and a common routine can be used in multiple locations by having an auxiliary page register, the capacity of the storage device can be reduced. Furthermore, even when the second word following the first word specifies a new instruction, such as an extended instruction whose instruction code spans two or more words, it can be handled simply by writing a microprogram. In addition, by making it possible to set and reset arbitrary bits in the auxiliary instruction register using microinstructions,
A special instruction in which each bit of the second word following the instruction code serves as a permission flag for the corresponding process can be processed at high speed with a small number of memory words.

〔Effect of the invention〕

As described above in detail, the present invention has a simple structure that does not use an instruction decoder.

It is possible to realize a microprogram control method that can be applied even to a complex instruction system in which the instruction code spans two or more words.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional microprogram control device, FIG. 2 is a diagram showing its time chart, FIG. 3 is a block diagram showing a conventional mapping method, and FIG. 4 is a diagram showing its time chart. FIG. 5 is a block diagram showing a microprogram control device according to the present invention, FIG. 6 is a diagram showing its time chart, FIGS. 7 and 10 are explanatory diagrams showing the configuration of a storage device, and FIG. FIG. 5 is a somewhat detailed block diagram, and FIG. 9 is an explanatory diagram showing the flow of processing. 14...Address register, 51...Page register. 71...AND circuit, 81...Auxiliary page register. Fig. 1 Fig. 3 Fig. 2 Fig. 4 Fig. Fig. Fig. Instruction reading routine/to Fig. Fig. 10

Claims (1)

[Claims] 1. Generate a first microprogram address from a first instruction word and first page specification information to access the microprogram memory, and the first instruction word has a certain specific value. In this case, the second instruction word following the first instruction word and second page specification information different from the first page specification information generate a second microprogram address and access the microprogram memory. A microprogram control method characterized by: 2. A microprogram control method according to claim 1, characterized in that the microprogram address is generated by directly placing an instruction word in a part of the microprogram address. 3. A first means for storing the microprogram divided into a plurality of page areas; and a second means for storing information specifying the page of the first means.
and a third means for storing addressing information in a page from which the instruction word can be directly taken in, and the third means specifies the first page and transfers the first instruction word to the third page. When the first instruction word has a certain value, the second instruction word that follows is read out, and a second page different from the second page is specified, and the second instruction word is read out. A microprogram control method characterized in that the program is incorporated into a third means.