JPH0333929A - Microprogram controller - Google Patents

Abstract

PURPOSE:To accelerate the execution speed of a microinstruction by reading out the microinstruction starting from the second step of a microinstruction memory, and interpolating a part during that time with the microinstruction at a first step from a constant generating part. CONSTITUTION:A prescribed microinstruction string is set by setting SRC as a source operand, DST as a destination operand, ALU as an instruction to set computation designation on an ALU 83, a signal (=) as a transfer instruction, and ENDM as the control instruction of program completion at the first step. The source and destination operands are transferred to registers TA81 and TB82, respectively with an instruction MI1 at the first step, and are computed with a computing element 83, and are stored in a register 84. After that, data in the register 84 is transferred to the destination operand with an instruction MI2 at the second step, then, a program is completed. Therefore, the instruction MI1 is generated at the first step with a constant generator 30, and the instruction MI2 at the second step is written on an MROM50.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and particularly to a microprocessor controlled by a microprogram (hereinafter referred to as a microprogram control device).

[Conventional technology]

In microprogram controllers, user programmable instructions are treated as macroinstructions, and each macroinstruction is processed by executing a corresponding series of microinstructions. A series of microinstructions corresponding to each macroinstruction is a microinstruction memory (hereinafter referred to as MROM).
is stored in. A macro instruction has address information in the MROM, and when a macro instruction to be executed is supplied, the address information specifies the start address of a series of corresponding micro instructions.

That is, address information possessed by a macroinstruction to be executed is loaded into a microaddress register, a predetermined location in the MROM is accessed based on the contents of the register, and the microinstruction at the same address is read out. The read microinstruction is latched into the microinstruction register. The microinstruction execution control unit decodes and executes the microinstructions latched in the microinstruction register. When the microinstruction read from the MROM is latched into the microinstruction register, the contents of the microaddress register are updated by l, the next address in the MROM is accessed, and the next microinstruction is read out. This microinstruction is loaded into the microinstruction register when the microinstruction execution control section finishes executing the previous microinstruction. When the execution of a series of microinstructions corresponding to the macroinstruction to be executed is completed, address information possessed by the macroinstruction to be executed next is loaded into the microaddress register.

[Problem to be solved by the invention]

In this way, in order to start execution of a series of microinstructions corresponding to each macroinstruction, the address information possessed by the macroinstruction to be executed is loaded into the microaddress register, the contents of the register are determined, and then M.R.
Preprocessing is required to read the first microinstruction from the OM.

Therefore, the start of execution of the series of microinstructions is delayed by this preprocessing period, and therefore the end of the series of microinstructions is delayed.

Accordingly, it is an object of the present invention to provide an improved microprogram controller.

Another object of the present invention is to provide a microprogram control device in which the microinstruction execution start point is brought forward and the overall microinstruction execution processing speed is increased.

[Means to solve the problem]

A microprogram control device according to the present invention includes a microinstruction memory that stores microinstructions, a microaddress register that temporarily stores address information for accessing a predetermined address of this memory, and a microinstruction register that temporarily stores microinstructions to be executed. an instruction register, a microinstruction execution control unit that executes the microinstructions held in this register, a constant generator that generates the first step microinstruction of a predetermined series of microinstructions, and a constant generator that executes the microinstructions read from the microinstruction memory. a selector for selecting either the issued microinstruction or the microinstruction generated from the constant generator; and a selector for loading predetermined address information into the microaddress register to perform the second step of the predetermined series of microinstructions. Before reading the microinstruction from the microinstruction memory and latching it in the microinstruction register, the first step microinstruction from the constant generator is held in the microinstruction register via the selector, and then the microinstruction is read from the memory. and control means for holding the second step microinstruction in the microinstruction register.

That is, in the present invention, the microinstructions read from the microinstruction memory are the second and subsequent steps of a series of microinstructions, and the period until the microinstructions are read from the memory is the first step microinstruction from the constant generator. It is interpolated with. Therefore, the execution of a series of microinstructions starts earlier, and the execution speed of the microinstructions as a whole becomes faster.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Macro instructions decoded by an instruction decode unit (IDU) (not shown) are stored in a decoded instruction queue (IDQ) 10 via a decoded instruction bus 5. IDQIO contains address information (STADQ) 1 of the microinstruction memory (MROM) 50 that the macroinstruction has.
1° Source operand information (S.

Destination operand information (DOPRNQ) 14 possessed by the macro instruction, and operation information (ALUFQ) 15 possessed by the macro instruction are stored. According to the present invention, IDQIO further stores information (SEQ) 12 as to whether a macroinstruction to be executed is processed by executing a routine series of microinstructions to be described later. When all the IDQIO information is collected, the IDU sends the ID to the microinstruction sequencer (MISEQ) 20.
The QIO valid signal (VQ) 6 is set to active level. When the MISEQ 20 is ready to start executing a microinstruction, the reception unit sets the signal (QACK) 7 to an active level to notify the IDU that it has received IDQIO information. MISEQ20 has an additional 5TA
DQI 1 is loaded into the micro address register (MA) 40 through the 5 multiplexer (MPX) and the corresponding MROM 50 is loaded.
access the address. The contents of Ma2O are incremented by 1 by the incrementer 48 and loaded into Ma2O via the MPX 44, thereby dealing with addressing of a series of microinstructions consisting of three or more steps.

Microinstructions read from MROM 60 are transferred to bus 55.
is supplied to one input of a selector (SEL) 60 via a bus 35, and the output from a constant generator (FIGEN) 30 provided according to the invention is supplied to the other input via a bus 35. The FIGEN 30 generates the first step microinstruction of a routine series of microinstructions under the control of the MISEQ 20. 5EL60 is MISEQ20
Based on the selection control signal 26 from
Select microinstructions from 5. The selected microinstruction is stored in the microinstruction register MI 80, which generates control signals 85 for reading/writing operands, and performs arithmetic and logic operations on the supplied operand data, an ALU 83, source and destination operands. Registers (TA) that temporarily store data
and TB) 82, 81, and a register (ALUO) 84 for temporarily storing the outputs of the ALU 83. Control information such as the microprogram execution start signal and execution end signal is transmitted via the control bus 88 between the MISEQ20 and the MICNT80.
It is done through. 5OPRNQI in IDQIO
3. DOPRNQl 4 and ALUFQl 5 are MI
It is supplied to CNT80.

In this embodiment, the first step microinstruction is a standard tabus (MD-
BUS) 90, the destination operand data specified by DOPRNQl4 is transferred from the second data bus (
SD-BUS) 95, performs the calculation specified by ALUFQI5 on these, and sends the calculation result to DOPRNQ1 through MD-BUS90.
A microinstruction sequence is set to write to the operand specified by 4. In this way, the source operand specified by the microphone, DST is the destination operand specified by DOPRNQI4, and ALU is the destination operand specified by DOPRNQI4.
The command "=" for setting the operation designation specified by Ql 05 in the ALU 83 is a command for performing transfer, and ENDM is a control command for terminating the execution of the microprogram. That is, the first step microinstruction (MII) sets the source and destination operands to TA82. At the same time, the ALU 83 executes the desired operation on these operands, stores the operation result in the ALUO 84, and then executes the second step microinstruction (MI2).
As a result, the data in the ALUO 84 is transferred to the destination operand, and the execution of this microphone program is completed. Therefore, the FIGEN 30 generates this first step microinstruction (MII), and the second step instruction (MI2) is written into the MROM 50.

The number of transfer gates (T
G). One end of each TG is connected to the power supply voltage V via a resistor R. . Alternatively, it is connected to the ground potential GND, and the other end is supplied to the 5EL60 as a bus 3501 bit. Each TG is opened by a signal 25 from M I S E Q20, and as a result, FIGEN30 converts the machine code of the first step microinstruction (Mll) to 5E.
Occurs at L60.

Now, as a macro instruction to be executed, an instruction processed by executing a series of microphone□ instructions shown in Fig. 3, for example, an instruction to add two operands, is decoded and ID
U is an MROM 50 in which the instruction MI2 of the second step in FIG. 3 is stored as 5TADQll in IDQIO.
address information ADDO is stored, and an addition command is stored as ALUFQl 5. Furthermore, since the macroinstruction is processed by a series of standard microinstructions shown in FIG. 3, information indicating "executable" is stored as 5EQ12. Furthermore, information indicating whether the operand is a memory operand or a register operand and data table information of the operand are provided in 5OPRN.
Ql 3. Store as DOPRNQI 4.

As is well known, the effective address of the operand is calculated in advance by an effective address generator (not shown), and the necessary operand is read out and sent to BUS9.
Operand register connected to 0,95 (not shown)
Stored in.

When all the information necessary for IDQIO is collected, the IDU sets VQ7 to an active high level in synchronization with the rise of the clock signal CLOOK, as shown in FIG. M.I.S.
In response, the EQ20 returns IDQACK7 to the IDU when the microinstruction becomes executable. M.I.S.
EQ20 further loads the contents of 5TADQII, that is, address information ADDO, into MA40 via MPX44, and starts reading out instruction MI2 from MROM50. At this time, the "executable" information of 5EQ12 in IDQIO is decoded by the decoder 21 in M I S E Q 20, and as a result, the signal 25.26
becomes an active high level for one clock. Therefore, the microinstruction Mll is generated from the FIGEN 30, and the microinstruction MII is latched into the MI 70 via the 5EL60. MICNT80 is such a microinstruction MII
Start decoding. During the period when the signals 25 and 26 are at the no-low level, the address ADDO of the MROM 50 is
The access to microinstruction M2 is completed and microinstruction M2 is read onto bus 55. Therefore, the microinstruction MI2 is latched into MI 70 via 5EL 60 by inverting signal 26 to a low level by the next clock. At the same time, execution of the microinstruction MII begins, and the fourth
As shown as "R" in the figure, the source and destination operand data are read into the MICNT 80, and the ALU 83 performs addition on both data. Since the macro instruction to be processed is executed as a two-step micro instruction, the output of the incrementer 44 is Ma
Loading into 2O is prohibited by signal 27. Microinstruction end command END owned by MI2
Since M has been transferred to MISEQ 20 via bus 88, MISEQ 20 is ready to accept the next macro instruction. Therefore, MISEQ20 is MI2 is MI7
It can respond to VQ6 generated while it is latched to 0 and returns IDQACK7 to the IDU. Assuming that such a macroinstruction is also executed according to the microinstruction sequence shown in FIG.
60 to MI70. 5TADQll
address ADDO is loaded into Ma2O. At the same time, execution of microinstruction MI2 is started, and ALU
The addition result in O84 is written back to the destination operand via MD-BUS 90, as shown as W'' in FIG.

In this way, before the address information specified by 5TADQII is loaded into Ma2O and the corresponding microinstruction MI2 is read out from MROM50, MI70
Since the first step microinstruction MII is latched, the execution of the series of microinstructions starts earlier.
Instruction execution speed can be improved.

Note that if the macro instruction to be executed cannot be processed by the series of micro instructions shown in Figure 3, 5TADQ
IDQI is the address information of the first microinstruction of a series of microinstructions corresponding to the macroinstruction to be executed as II.
0, and "unexecutable" information is stored as 5EQ12. In this case, since the signals 25 and 26 remain at the low level, the first step instruction of the series of microinstructions to be executed is latched into the MI 70 one clock after the address is loaded into Ma2O.

Next, a second embodiment of the present invention will be described.

In the 7 dressing mode of the macro instruction, modification of a specific register may be specified. For example, the contents of a specific register are used as an operand address, the address is modified (ie, increased or decreased) by a predetermined value, and the data addressed by that value is loaded into another register.

Register modification in this case can also be performed using the microphone □ command generated by the constant generator described above. A microprogram for register modification is shown in FIG. 6, for example. In Figure 6, MODRE
G is the register to be modified, ■NCDEC is an instruction to set the operation specification to the arithmetic unit in the microprogram control unit to increase or decrease the contents of the register to be modified by the amount of modification, and RESTART is the instruction to end the register modification operation. and 5TA in IDQ
This is a control command for starting the execution of a microprogram from the address specified by DQ, and the rest is the same as in FIG. 3. That is, the contents of the register to be modified are loaded into TA by microinstruction MI 10 in the first step, and an operation to increase or decrease by the specified modification amount is executed, and the result of the operation is stored in ALUO. , the operation result is written back to the register to be modified by microinstruction MIII in the second step, and an instruction is activated using the modified register. The register modifying operation shown in Fig. 6 can also be completed with a typical two-step microprogram, so the second step microinstruction Mll is read out from the MROM, and at the same time the first step microinstruction MIO is read out by the constant generator. By generating and executing the microprograms, the microprograms can be executed more quickly than when all the microprograms corresponding to the register modifying microprograms and macro instructions are read out from the MROM.

can also end one clock earlier. Therefore, the execution speed of the entire processor can be reduced. In addition, the microinstructions generated by the constant generator are the same as the microinstructions stored in the MROM, so there is no need to provide a special sequence circuit to execute a typical microprogram, and the microinstructions generated by the constant generator are the same as those stored in the MROM. A microprogram can be executed using the program control circuit as is.

FIG. 8 shows a third embodiment of the present invention. This embodiment has both the functions of the previous two embodiments. That is, FIGEN30 is the microinstruction MII in FIG.
and the microinstruction M110 shown in FIG. 6 can be generated, and when the signal 25-1 is at a high level, the microinstruction MII is supplied to the 5EL60, and when the signal 25-2 is at a high level, the microinstruction M110 is supplied to the 5EL60. signal 25
-1 is generated by an AND gate 29 receiving the output of decoder 21 and the inverted output of decoder 22;
-2 is generated by AND gate 23 shown in FIG. OR gate 26 receiving signals 25-1, 25-2
1 generates a selection signal 26 for 5EL60. Therefore, when the macro instruction to be executed can be executed using the microinstruction sequence shown in FIG. 3, the same operation as in the first embodiment is obtained, and when the macro instruction to be executed has an addressing mode that involves register modification. The same operation as the second embodiment can be obtained.

Among the macro instructions to be executed, in addition to arithmetic and logical operation instructions for double operand data and instructions with an addressing mode that involves register modification, there are also comparison instructions that do not write operation results back to the destination operand, and There are various instructions, such as a single operand instruction that adds or subtracts a constant "l" to a destination operand, a data transfer instruction between registers, between memories, or between registers and memories, and no-operand instructions such as branch instructions. The FIGEN 30 can also generate the first step microinstruction of a series of microinstructions corresponding to these macroinstructions. However, in order to provide the FIGEN 30 with a large number of micro-instructions, a memory cell array configuration has to be adopted, and since the reading period of the micro-instructions from the MROM 50 is interpolated, there is no point in providing the FIGEN 30.

Therefore, a configuration for executing the above-mentioned comparison instruction, single-operand instruction, etc. using the microinstruction sequence shown in FIG. 3 will be described below. In the following description, in order to avoid redundancy in the description and drawings, only characteristic parts are shown, and for the rest of the configuration, please refer to FIG. 1.

FIG. 9 shows a macro instruction of a comparison instruction, and when the instruction is decoded, "comparison operation" information is stored as ALUFQl 5. This information is decoded by the decoder 200, and the write inhibit signal 201 to the 5D-BUS 95 becomes active level. When the microinstruction MII shown in FIG. 3 is executed, the control signal 85 reads the source operand data from the MD-BUS 90 and the destination operand data from the 5D-BUS 95, and performs the comparison operation specified by ALUFQl 05. will be carried out. Since the write inhibit signal 121 to the 5D-BUS 95 is active during the execution of the microinstruction MI2 in the second step, the control signal 85 for writing back the comparison operation result to the destination is not generated, and as a result, Execution of the microprogram ends without writing back to the destination. On the other hand, if the write prohibition signal 121 to the 5D-BUS 95 is inactive, writing to the destination is performed as usual, and the execution of the microprogram ends.

FIG. 10 is for a single operand instruction that adds or subtracts a constant "1" to operand data. When the execution of the microprogram shown in Fig. 3 starts, IDQIO
The information set in ALUFQl 5 in MICNT8
0 and the selector with decoder 300
Decode the calculation information of ALUFQl5 with
If the operation information set in I 5 is "addition or subtraction of l," specify the constant "1" generator 300 as the source operand and pass it to the MICNT 80. If the operation information set in ALUFQl 5 is not "addition or subtraction of 1." is 5OPRN
Pass the information in Q13 as is to MI CNT80. MD-B at the first step (MII) of the microprogram
The source operand data indicated by the information of 5OPRNQ13 or the constant "1'" generated by the constant "1" generator 300 is read from the US90, and the destination operand data is read from the 5D-BUS95, and the ALUFQl The operation specified in 05 is performed. Then, the second step (MI2) of the microprogram
At this point, writing to the 5D-BUS 95 is performed, and the execution of the microprogram ends.

FIG. 11 is for a data transfer command.

If the decoded macro instruction is a transfer instruction, the IDU adds information indicating "reading not possible" to DOPRNQl 4 in addition to specifying the operand. Decoder 4
00 is the read inhibit signal 401 of SD-BUS 95 by decoding the information of DOPRNQI O4
is set to active level and passed to (MI CNT 116. Therefore, the first step microinstruction MII
In the execution of the instruction MII, the read inhibit signal 401 is active, so the control signal 85 for reading the destination data is not generated, and the operation when executing the instruction MII is performed using the source operand data read from the MD-BUS 90. This is done between the undefined values remaining in the register TB (FIG. 1).

However, in transfer-related macro instructions, operations that are not affected by destination data (outputting source data as is, taking two's complement of source data, etc.)
is specified by the IDU, the correct value can be obtained as the calculation result. The result of this operation is written to the destination specified by DOPRNQl 04, and the execution of the microprogram ends.

FIG. 12 is for a no-operand instruction such as a branch instruction. If it is a macro instruction like this, the ID
U is 5OPRNQ13 and ri.

Information called 'invalid operand' is set for PRNQ14. The first decoder 500 and the second decoder 600
If “is not an invalid operand, leave it as is MICNT8”
However, if it is an 'invalid operand', it is converted to information indicating an internal resource that does not affect the execution of the microprogram and is passed to the MICNTI 16.As an example of an internal resource that does not affect the execution of the microprogram. teeth,
There are MD-BUS90 and 5D-BUS95 themselves.

When executing a macroinstruction without operands using the microprogram shown in the embodiment of this invention, MD-BUS
Source data is read from 5D-BUS 90 and destination data is read from 5D-BUS 95, and since the calculation specification from the IDU is undefined, some undefined calculation is performed.
The calculation result is written to the MD-busl 18, and the execution of the microprogram is completed.

〔Effect of the invention〕

As described above, in the present invention, a typical microprogram is generated as a constant, and the first step of the microprogram is generated and executed by the constant generator during the period of reading out the second and subsequent microinstructions of the microprogram from the MROM. By doing so, compared to the case where all the microinstructions constituting the microprogram are read from the MROM, the execution of the microprogram is accelerated by one clock, thereby shortening the execution time of the macroinstruction. Furthermore, since the operation specification of the macro instruction is decoded and the write-protection instruction of the operand or the specified operand is changed, the same microprogram as the one that implements the operation-related macro instruction can be used to write the comparison-related macro instruction and the single It is possible to implement macro instructions with operands. I
For the DU side, the number of macro instructions that can be implemented with standard microprograms will increase, and the same address information (STADQ information) will be assigned to the macro instructions that can be executed with these standard microprograms. Therefore, if you use arithmetic macro instructions, transfer macro instructions, or operandless macro instructions, you can
It can be expected that the IDU circuit scale can be reduced compared to the case where TADQ is used.

[Brief explanation of drawings]

Figure 1 is a block diagram of the first embodiment of the present invention, Figure 2 is an internal configuration diagram of the constant generator (FIGEN) in Figure 1, and Figure 3 is a block diagram of the first embodiment of the present invention.
4 is a timing diagram showing the operation of FIG. 1, FIG. 5 is a block diagram of the second embodiment of the present invention, and FIG. 6 is a block diagram of the second embodiment of the present invention. 7 is a timing diagram showing the operation of the second embodiment; FIG. 8 is a block diagram showing the third embodiment of the present invention; FIGS. 9 to 12 2A and 2B are partial block diagrams according to further embodiments of the present invention, respectively.

Claims (2)

[Claims] (1) A microinstruction memory that stores microinstructions;
a micro-address register that temporarily stores address information for specifying a predetermined address of this memory, a micro-instruction register that temporarily holds micro-instructions to be executed, and an execution unit that executes the micro-instructions held in this register; Selecting a constant generator that generates a first step microinstruction of a predetermined series of microinstructions, and selecting one of a microinstruction read from the microinstruction memory and a microinstruction generated from the constant generator. a selector, and the constant before loading predetermined address information into the micro-address register and reading out the second step micro-instruction of the predetermined series of micro-instructions from the micro-instruction memory and holding it in the micro-instruction register. Control for holding the first step microinstruction from a generator in the microinstruction register via the selector, and then holding the second step microinstruction in the microinstruction register via the selector. A microprogram controller comprising means. (2) means for holding operand information of a macro instruction; and means for holding operation information of a macro instruction;
a decoder that decodes the calculation information held in the calculation information holding means; a microinstruction memory in which microinstructions are stored; a constant generator that generates a specific microinstruction; and a microinstruction read from the microinstruction memory. and a selector for selecting one of the microinstructions generated from the constant generator, a means for converting the operand information held in the operand information holding means into another operand information, and a microinstruction to be actually executed. A microprogram generated by the constant generator during a period from reading a microinstruction to be executed in the second step of the microprogram from the microinstruction memory to latching it in the microinstruction latch. The micro instruction is latched in the micro instruction latch and executed, and then the second step micro instruction is executed, and the operand conversion means is controlled by the decoder output of the operation information. Program control device.