JPH03164945A - Data processor - Google Patents

Abstract

PURPOSE:To facilitate the program debugging operations by storing only a single instruction into an instruction queue in a trace mode and evading the unnecessary memory accesses. CONSTITUTION:In a trace mode a trace mode signal 31 outputted from an instruction executing part 3 is validated, and an instruction fetch switching circuit 13 selects a trace mode fetch request signal 14 received from an instruc tion decoding part 2 and gives it to an instruction fetch control circuit 12. The circuit 12 fetches only a single word and stores it in an instruction queue 11 every time the signal 14 is validated. Thus just the necessary number of instruction codes are fetched in the trace mode in response to the decoding result of the part 2. As a result, only the instruction codes corresponding to a single instruction are fetched by an instruction fetching part and stored there. Thus the program debugging operations can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and more specifically, the present invention relates to a data processing device that is equipped with a pipeline processing mechanism and that processes variable length instructions into one instruction for program debugging, etc. The present invention relates to a data processing device capable of executing a trace mode executed by a pipeline processing mechanism.

[Conventional technology]

A pipeline processing mechanism is generally employed to increase the processing speed of a data processing device.

FIG. 2 is a block diagram showing the configuration of the main parts of a conventional data processing apparatus having a general pipeline processing mechanism.

In the figure, reference numeral 1 is an instruction fetch unit that fetches instruction codes from an instruction memory (not shown) via a data bus 6.The instruction fetch unit 1 includes an instruction queue that temporarily stores the fetched instruction codes. 11, and an instruction fetch control circuit 12 that executes control for fetching instructions.

Reference numeral 2 denotes an instruction decoding section, which decodes the instruction code stored in the instruction queue 11 and provides the result to the instruction execution section 3.

The instruction execution unit 3 actually executes the instruction according to the decoding result of the instruction code.

The operation of such a conventional data processing device is as follows.

The instruction fetch unit 1 fetches an instruction code from an instruction memory (not shown) via the data bus 6 under the control of the instruction fetch control circuit 12, and stores it in the instruction queue 11.

The instruction 5 phantom J-code unit 2 takes out the instruction code stored in the instruction 1-knee 11, decodes it, and outputs the decoding result to the instruction execution unit 3.

The instruction execution unit 3 executes an operation according to the decoding result given from the instruction decoding unit 2, and transfers the operation result to the address bus 7 where the operation result is stored, and the data of the operation result to the data bus 6, as necessary. By outputting, it is written to memory etc.

In this way, in a data processing device with a pipeline processing mechanism, the processing specified by each instruction is broken down into three steps: fetch, decode, and execution, and each step is processed sequentially to execute the process. be done. Since the processing in each step can be executed in parallel, for example, while the first instruction is being processed in the instruction execution unit 3, the second instruction is decoded in the instruction decoding unit 2, and the third instruction is processed in the instruction decoding unit 2. is fetched from the instruction memory in the instruction fetch unit 1, and so on.
It becomes possible to simultaneously execute multiple instructions in parallel using a pipeline processing mechanism.

Therefore, the three-step pipeline processing mechanism shown in FIG. 2 generally exhibits a processing capacity of 34@ compared to a data processing device that does not have a pipeline processing mechanism.

Furthermore, memory access, that is, reading instruction data etc. from memory and loading data into memory is generally slower than processing in a pipeline processing mechanism. Therefore, in order to absorb the difference between the speed at which the instruction code is fetched from the memory by the instruction queue 11 and the speed at which the instruction code is processed at the instruction decoding section 2, the instruction queue 11 stores the instructions as much as possible. As long as there is space in the queue 11 and the data bus 6 can be used, the instruction code is pre-fetched from the instruction memory.

By the way, in a data processing apparatus having a pipeline processing mechanism as described above, for the purpose of debugging a program or the like, only one instruction may be taken into the pipeline processing mechanism and executed sequentially. This instruction processing state is called trace mode, while the state in which pipeline processing is performed by each step of the pipeline processing mechanism described above is called normal mode.

In the trace mode, the instruction fetch unit l fetches an instruction code from the instruction memory and stores it in the instruction queue 11, as in the normal mode.

The instruction decoding section 2 takes out the instruction code stored in the instruction queue 11, decodes it, and outputs the decoding result to the instruction execution section 3. Thereafter, the instruction decoding section 2 does not decode other instruction codes until the instruction execution section 3 completes processing for this decoding result.

The instruction execution unit 3 executes a specified operation according to the decoding result of the instruction code given from the instruction decoding unit 2,
Writing the calculation results to memory as necessary is the same as in the normal mode.

[Problem to be solved by the invention]

In a data processing device having a conventional pipeline processing mechanism as described above, when handling an instruction whose instruction code length is not fixed (variable length instruction), the instruction decoding unit 2 decodes the instruction by decoding the instruction by decoding the instruction by decoding it in the instruction decoding unit 2. The length of the instruction cannot be known until after the instruction is executed.For this reason, instruction codes are taken into the instruction queue 11 in the trace mode in the same way as in the normal mode.

In this way, during trace mode, the instruction queue 11
In a conventional data processing device in which instruction codes are fetched in the same way as in normal mode, if there is a bug in the program and an error occurs as a result of execution in the instruction execution unit 3, multiple instructions are stored in the instruction queue 11. instruction codes are stored, so it is not easy to identify the instruction that caused the error, and it is difficult to debug the program.

The present invention was made in view of these circumstances, and
l. In race mode, only one instruction to be executed on the pipeline processing mechanism is stored in the instruction queue 11, and unnecessary memory access is not performed. This is a program for when an error occurs in the instruction execution section. The purpose of this invention is to provide a data processing device that facilitates debugging.

[Means to solve the problem]

In the trace mode in which instructions are processed one by one by the pipeline processing mechanism, the data processing device of the present invention provides control to cause the instruction fetch unit to fetch instruction codes one unit at a time according to the decoding result in the instruction decoding unit. Equipped with a circuit.

[Effect]

In the data processing device of the present invention, in the I-race mode, as many instruction codes as necessary are fetched according to the decoding result in the instruction decoding section, so only the instruction codes corresponding to l instructions are fetched into the instruction fetch section. and stored.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

Note that the instructions handled by the data processing device of the present invention have a variable length in halfword units. One word is a certain length (eg, 16 bytes, 2 bytes, etc.) to represent the length of an instruction code.

Further, each instruction is composed of an operation code for specifying an operation to be executed, and an operand representing information regarding data to be subjected to the operation.

The operation code can be specified as 1 halfword, the operand can be specified as O to 2 halfwords, and therefore the instruction length is between 1 halfword and 3 halfwords.

FIG. 1 is a block diagram showing an example of the configuration of essential parts of a data processing device according to the present invention.

In the figure, reference numeral 1 is an instruction fetch section, which fetches instruction codes from an instruction memory (not shown) via a data bus 6.

The instruction fetch unit 1 stores 4 fetched instruction codes.
An instruction queue 11 that can temporarily store up to words (8 half words), an instruction fetch control circuit 12 that executes control for fetching instructions, and an instruction fetch switching circuit 13
and are included. Note that the instruction queue 11 is indicated by the broken line 8.
It is divided into equal parts, which means that each partition has a capacity to store l halfwords.

The instruction fetch unit 1 starts processing upon receiving a platinum processing start signal 32 output from the instruction execution unit 3, which will be described later.

Further, the instruction fetch switching circuit 13 is supplied with a normal fetch request signal 15 from the instruction unit 11, a trace mode signal 31 from the instruction execution section 3, and a trace mode fetch request signal 14 from the instruction decoding section 2, which will be described later. , gives instructions to the instruction fetch control circuit 12 according to these signals.

Specifically, the instruction fetch switching circuit 13 includes two 2-man-powered AND gates 21 and 22 and one 2-man-powered NOR gate 2.
It is composed of 3.

One input of the first ^ND gate 21 receives the normal fetch request signal 15, and the other input receives the trace mode signal 3.
An inverted signal of 1 is given. Second ^ND gate 2
Trace mode fetch request signal 1 is input to one input of 2.
4, and a trace mode signal 31 is applied to the other input. The outputs of both AND gates 21 and 22 are applied to both inputs of the N0II gate 23, and the output of the NOR gate 23 is applied to the instruction fetch control circuit 12.

Therefore, the trace mode signal 31 is
In this case, the first AND gate 21 is enabled, so that when the normal fetch request signal 15 becomes valid (high level), it is given to the instruction fetch control circuit 12. On the other hand, when the trace mode signal 31 is valid, the second AND gate 22 is enabled, so when the trace mode fetch request signal 14 becomes valid, it is applied to the instruction fetch control circuit 12.

Reference numeral 2 denotes an instruction decoding section, which decodes the instruction code stored in the instruction queue 11 and provides the result to the instruction execution section 3. The instruction decode unit 2 also includes an instruction execution unit 3.
trace mote signal 31 and instruction processing start signal 32
are also given, and in accordance with these signals and its own decoding processing state, in the trace mode, it outputs a trace mode fetch request signal 14 requesting the instruction fetch unit 1 to fetch in l word units.

The instruction execution unit 3 actually executes the instruction according to the decoding result of the instruction code. It also outputs a trace mode signal 31 and an instruction processing start signal 32 to the instruction fetch section 1 and instruction decode section 2.

The operation of the data processing apparatus of the present invention configured as described above is as follows.

When an instruction processing start signal 32 is output from the instruction execution section 3, this signal is given to the instruction processor 1 and the instruction decode section 2 to start processing.

In normal mode, trace mode signal 31 is disabled. Then, the instruction fetch unit 1 fetches an instruction code from an instruction memory (not shown) via the data bus 6 under the control of the instruction fair control circuit 12,
Store it in the instruction queue 11.

Fetching of the instruction code by this instruction fetch unit l is as follows:
As long as there is space in the instruction queue 11, the process is repeated one word at a time using the time when the data bus 6 is free.

Specifically, if there is space in the instruction queue 11, the instruction queue 11 outputs the normal fetch request signal 15 to the instruction fetch switching circuit 13, but since the I/racemoto signal 31 is invalid, the instruction fetch switching circuit 13 outputs the normal fetch request signal 15. 13 selects the normal fetch request signal 15 and sends the instruction fetch control circuit 12
give to As a result, each time the instruction queue control circuit 12 outputs the normal fetch request signal 15 from the instruction queue 11, ! The instruction code is fetched at about 1 m and stored in the instruction queue 11. At this time, if there is more space in the instruction queue 1, the instruction queue 11 outputs the normal fetch request signal 15 again, so the instruction fetch control circuit 12 fetches one more word.

The instruction decoding section 2 extracts and decodes the instruction code stored in the instruction keys 1-11, and outputs the decoding result to the instruction execution section 3.

The decoding of the instruction code by the instruction decoding section 2 is as follows:
First, one word of the operation code is taken out from the instruction queue 11 and decoded, and if necessary, the number of words of the operand is determined. Next, a necessary operand is taken out from the instruction queue 11, decoded, and output to the instruction execution unit 3 together with the decoded result of the previous operation code.

The instruction execution section 3 executes an operation according to the decoding result given from the instruction decoding section 2, and outputs the address of the storage destination of the operation result to the address bus 7 and outputs the data of the operation result to the data bus 6 as necessary. By doing this, it is written to memory etc.

As described above, in the data processing device of the present invention, in the normal mode, the instruction fetch unit 1. Since the instruction decoding unit 2 and the instruction execution unit 3 each execute processing independently, for example, while the first instruction is being processed in the instruction execution unit 3, the second execution is decoded in the instruction decoding unit 2, As the third instruction is fetched from the instruction memory in the instruction fetch unit 1, it becomes possible to execute a plurality of instructions simultaneously in the pipeline processing mechanism.

Therefore, the three-step pipeline processing mechanism shown in FIG. 1 generally exhibits three times the processing power as compared to a data processing device that does not have a pipeline processing mechanism.

In the trace mode, the trace mode signal 31 output from the instruction execution unit 3 becomes valid.

When the first-race mode signal 31 becomes valid, the instruction fetch switching circuit 13 selects the trace mode fetch request signal 14 output from the instruction decoder 2 and supplies it to the instruction fetch control circuit 12.

The instruction fetch unit 1 fetches the instruction code from the instruction memory and stores it in the instruction queue 11 as in the normal mode, but the control at this time is controlled by the l/race mode signal 31, and the trace mode fetch request signal 14
Each time the instruction fetch control circuit 12 becomes valid, the instruction fetch control circuit 12
Only words are fetched and stored in the instruction queue 11.

The instruction decoding unit 2 extracts and decodes a halfword corresponding to the operation code portion of the instruction code stored in the instruction queue 11.

If the decoded result requires two halfwords of operands, there are only l halfwords left in Instruction Queue II (one word was fetched first, then one halfword for the operation code). (word has already been fetched into the instruction decode unit 2), the instruction decode unit 2 again outputs the trace mode fetch request signal I.
Outputs 4.

When the trace mode fetch request signal 14 is output again, the instruction fetch unit 1 fetches the next word and stores it in the instruction queue 11.

Now, the instruction queue 11 stores 3-words, so the instruction decoder 2 takes out 2-words, decodes them, and executes the instruction along with the decoding result of the previous operation code. Output to section 3.

Further, when the trace mode signal 31 output from the instruction execution unit 3 is valid, the instruction decoding unit 2 performs
After the decoding of an instruction is completed, decoding of other instruction codes is not performed until the processing of the decoding result in the instruction execution unit 3 is completed.

The instruction execution unit 3 performs a specified operation on the decoding result of the instruction code given from the instruction decoder unit 2,
Writing the calculation results to memory as necessary is the same as in the normal mode.

When execution processing for one instruction is completed, an instruction processing start signal 32 is output. By outputting this instruction processing start signal 32, the instruction fetch section 1 and the instruction decoding section 2 re-execute the processing in the trace mode as described above.

In the second embodiment, the pipeline processor (11) is composed of three steps: an instruction fetch section 1, an instruction decoder section 2, and an instruction execution section 3, but the data processor is composed of even more steps. The present invention is also applicable to processing devices.

〔Effect of the invention〕

As described above, in the data processing device of the present invention, in the normal mode, the instruction fetch section, instruction decode section, and instruction execution section independently operate in parallel to perform pipeline processing on a plurality of instructions. In the trace mode, only the instruction code of one instruction is fetched, decoded, and executed. Therefore, only necessary memory accesses are performed and unnecessary memory accesses are not performed, making program dehasing easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a data processing device according to the present invention, and FIG. 2 is a block diagram showing a configuration example of a data processing device having a conventional pipeline processing mechanism. 1... Instruction f, y-'7chi section 2... Instruction decoding section 3... Instruction execution section 11... Instruction queue
12... Instruction fetch control circuit 13... Instruction fetch switching circuit Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) An instruction fetch unit that divides a variable-length instruction into predetermined units and pre-fetches it; a storage unit that temporarily stores the instructions pre-fetched by the instruction fetch unit; and a storage unit that temporarily stores instructions stored in the storage unit. In a data processing device that performs pipeline processing of instructions by a pipeline processing mechanism having an instruction decoding unit that decodes an instruction and an instruction execution unit that executes an instruction according to a decoding result by the instruction decoding unit, During trace mode, which starts processing the next instruction after processing is completed,
A data processing device comprising: a control circuit that causes the instruction fetch section to fetch the next unit according to a decoding result of the instruction decoding section.