JPH08297583A - Processor and method for interruption processing - Google Patents

Abstract

PURPOSE: To provide an interruption device which performs processing without branching after accepting an interruption at an interruption request that can be processed with several instructions by slight alteration of hardware, and automatically returns to the original program after the instruction execution. CONSTITUTION: After an interruption request signal 130 is inputted to an interruption control part 140, a switching means 150 changes an instruction code inputted to an instruction decoder 160 into an instruction code held in a storage means 120 and holds the value of a program counter 110 at the same time. After a specified program was executed, the output of the switching means 150 is put back and the program counter 110 begins to be updated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing device and interrupt method for a processor.

[0002]

2. Description of the Related Art With the rapid development of digital technology in recent years, a processor (DSP) capable of executing high-level processing such as digital signal processing at high speed has been required. DSP
Must perform processing in response to processing requests from various peripheral devices as fast as possible. The number of peripheral devices connected to the DSP is increasing as the system becomes more complicated, and the operation speed is also increasing. That is, it is necessary to start the processing corresponding to various processing requests in a short time from the time when the requests are input, and to immediately return to the original processing when the processing is completed.

Conventionally, these new processes are realized by interrupt processing. In this case, the start of the new processing / return to the original processing is fixed depending on 1, the acceptance of the interrupt request, and the type of the interrupt request. Branch to address X of the program memory, 3, Branch to the first address Y of the program corresponding to the interrupt request input by the branch instruction held at the memory address X, execute process 4, return to the original process It was common to go through the step of branching (for example, "MN 1920 Series LSI Manual, page 5-89 (1
990, published by Matsushita Electronics Industrial Co., Ltd.) ").

The interrupt in the above conventional technique will be briefly described below. First, the interrupt control circuit inside the DSP receives the interrupt request signal.

Next, the interrupt controller which receives the request outputs the address data X (generally called an interrupt vector) determined by the type of interrupt to the data bus. At the same time, an interrupt instruction is issued to the instruction decoder. The interrupt instruction controls the start of interrupt processing. That is, write the data of the data bus to the program counter,
The value of the program counter before updating is saved in the stack memory. As a result, the address X corresponding to the interrupt request
The branch to is executed.

At the address X, there is an instruction that branches to the head address Y of the program to be actually processed, the branch instruction is executed, and then the program execution is started.

When the interrupt processing is completed, the original program is restored by referring to the value of the program counter saved in the stack memory.

[0008]

However, since DSP generally performs pipeline processing in order to realize high-speed throughput, an overhead of several instructions occurs at each branch. That is, after inputting an interrupt request,
An overhead occurs because of branch operations unrelated to the original processing such as branching to an interrupt vector, branching to a program to be executed by an interrupt request, and branching to the original program. With the above configuration / method, the overhead can be ignored if the program has a very large interrupt process, but prompt response is required, and data transfer to a certain control register (such as turning on the I / O port) is required. There is a problem that the overhead is larger for the processing of a certain single instruction and a high-speed interrupt response cannot be performed.

In view of the above points, the present invention executes an interrupt request that can be processed by several instructions with a slight change of hardware, executes the processing without branching after the acceptance of the interrupt, and automatically executes the original processing after the execution of the instruction. An object of the present invention is to provide an interrupt processing device that returns to a program and a method thereof.

[0010]

SUMMARY OF THE INVENTION An interrupt processing device of the present invention indicates a storage means connected to a data bus and readable / writable by a program, a program memory for storing the program, and an access address of the program memory. A first program counter, a signal switching means that is connected to the program memory and the storage means and selects and outputs any one of the outputs, and outputs a selection signal to the switching means in response to an interrupt request, The interrupt control means for outputting the update stop signal to the first program counter and the instruction decoder connected to the switching means for decoding the instruction code of the output are provided, whereby the above object can be achieved.

The interrupt control means further has a second program counter therein, operates the second program counter in response to an interrupt request, counts a preset number of times, and then selects to the switching means. A signal and a function of stopping the output of the update stop signal to the first program counter may be provided.

The interrupt control means may further have a function of outputting the address indicated by the second program counter.

The storage means may have a function of outputting an instruction code stored according to an address output from the interrupt control section.

The interrupt control means may further have a function of outputting different addresses corresponding to a plurality of interrupt requests.

According to the interrupt processing method of the present invention, the control of the program is changed by stopping the update of the program counter for instructing the access address of the program memory in response to the interrupt request and changing the selection of the switching means to the storage means side at the same time. As a result, the above object is achieved.

The processing method may be achieved by further changing the selection made by the switching means to the program memory side after the preset number of times of execution of the program and restarting the updating of the program counter.

By changing the program stored in the storage means, it is possible to achieve different processes with the same interrupt request.

[0018]

According to the present invention, after the interrupt request is input to the interrupt control unit, the switching unit changes the instruction code to be input to the instruction decoder and simultaneously holds the value of the program counter. After the predetermined program is executed, the output of the switching means is returned to the original state and the update of the program counter is restarted.

[0019]

【Example】

(Embodiment 1) An interrupt processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows a block diagram of an interrupt processing apparatus according to this embodiment.

In FIG. 1, 100 is a program memory for storing programs, and 105 is a program memory 10.
Command output from 0, 110 is program memory 10
Program counter that outputs access address to 0, 12
Reference numeral 0 is a register for holding a program to be executed in response to an interrupt request, and 125 is an instruction output from the register 120.

In response to the interrupt request signal 130, 140 outputs a selection signal 141 for giving selection information to the multiplexer 150, which will be described later, to the multiplexer 150, which serves as switching means, which will be described later, and causes the program counter 110 to stop the program counter 110. It is an interrupt control unit that outputs a control signal 142 that gives information.

Reference numeral 150 denotes a multiplexer for switching between the instruction 105 and the instruction 125 by a selection signal 141 and outputting them.
55 is an instruction output from the multiplexer 150, 160
Is a decoder for decoding the instruction 155, 170 is a register 1
20 is a data bus for exchanging data between 20 and other storage means (not shown).

In the above, the data bus 170 is 16 bits,
The instruction word length is 24 bits. However, the data bus and instruction word length of the present invention are not limited to them. Also, 1
Although 20 is used as a register, it may be mapped in the memory.

The operation from the input of an interrupt request to the start of execution of the program corresponding to the interrupt request in the interrupt processing device of the present embodiment configured as described above is shown in FIG.
Will be explained.

First, in step 1, the interrupt request 13
The instruction code to be executed by 0 is stored in the register 120. The structure of the register 120 is shown in FIG. That is, it consists of two 16-bit registers 121 and 122,
Each of the three registers is connected to the data bus 170 and can be read / written through the data bus 170. The lower 16 bits of the instruction code are stored in the register 121, and the upper 8 bits of the instruction code are stored in the lower 8 bits of the register 122. As shown in FIG. 2, the output of the register 120 corresponds to the lower 8 bits of the register 122 to all bits of the register 121. Therefore, in step 1, the register 12 is divided into two by the transfer instruction.
1. Store the instruction code in the register 122.

Thereafter, in step 2, the interrupt request 13
0 is input to the interrupt control unit 140. If the interrupt request 130 uses the instruction stored in the register 120, the interrupt control circuit 140 uses the multiplexer 1
"1" is output as the selection signal 141 to 50, and "1" is output as the control signal 142 to the program counter 110. The program counter 110 holds the value by the value "1" of the control signal 142. The multiplexer 150 selects and outputs the instruction 125 according to the value “1” of the selection signal 141. When the value of the selection signal 141 is "0", the instruction 105 is selected. The instruction decoder 160 uses the instruction 155, that is, the interrupt request 130.
Decode the instruction corresponding to. As a result, the processing corresponding to the interrupt request 130 is performed without overhead.

After one instruction cycle, the interrupt control unit 140 sets the selection signal 141 to "0" and the control signal 142 to "0", and outputs it. The program counter 110 inputs "0" of the control signal 142 and starts updating the held access address, and the multiplexer 150 inputs "0" of the selection signal 141 to select the instruction 105. As a result, the original program can be restored without a branch instruction.

(Embodiment 2) An interrupt processing device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of the interrupt processing device according to this embodiment.

In FIG. 3, the register 120 is the register 220, and the interrupt controller 140 is the interrupt controller 24.
The configuration is the same as that of the interrupt processing device shown in FIG. 1 except that 0 is replaced and an address 245 is added. Therefore, description of the components other than the register 220, the interrupt control unit 240, and the address 245 will be omitted.

Reference numeral 220 outputs a selection signal for selecting an instruction in accordance with an address signal 245 indicating which instruction code of a plurality of instructions to output, and internally has an address decoder 227 and a multiplexer 228 as shown in FIG. A register 240 is the interrupt control unit 14 of the first embodiment.
In addition to the function of 0, the interrupt control unit has a program counter function therein, outputs an address 245 to the register 220 according to the value of the counter, and has a function of detecting a preset address.

In the above, the data bus is 16 bits and the instruction word length is 24 bits. However, the data bus and instruction word length of the present invention are not limited to them. Although 220 is used as a register, it may be mapped inside the memory.

The operation from the input of an interrupt request to the start of execution of the program corresponding to the interrupt request in the interrupt processing device of the present embodiment configured as described above is shown in FIG.
Will be explained.

First, in step 1, the interrupt request 13
The register 220 stores a plurality of instruction codes to be executed by 0.
In order. Here, there are three instructions. However, the number of instructions is not limited to three. In that case, an address and a program counter that match the number of instructions to be executed are prepared, and the number of registers 220 is prepared. The structure of the register 220 is shown in FIG. That is, six 16-bit registers 22
1 to a register 226. Six registers are connected to the data bus 170 and can be read / written through the data bus 170. The lower 16 bits of the first instruction code of the instruction to be executed in the interrupt process are stored in the register 221, and the upper 8 bits are stored in the lower 8 bits of the register 222. Similarly, the lower 16 bits of the instruction code of the second instruction to be executed in the interrupt process are stored in the register 223, the upper 8 bits are stored in the lower 8 bits of the register 224, and the lower 1 of the instruction code of the third instruction is stored.
The 6 bits are stored in the register 225 and the upper 8 bits are stored in the lower 8 bits of the register 226. The output of the register 220 is, as shown in FIG. 4, the lower 8 bits of the register 222 and all the bits of the register 221, or the register 2
Lower 8 bits of 24 and all bits of register 223, or lower 8 bits of register 226 and register 22
Any of all 5 bits is selected by the address signal 245 (which becomes a selection signal via the decoder 227). Therefore, in step 1, the data is stored in the register 220 in six steps according to the transfer instruction.

Next, in step 2, the interrupt controller 24
The number of instructions "3" is set in the setting register within 0. After that, the interrupt request 130 is input to the interrupt control unit 240. If the interrupt request 130 uses the instruction stored in the register 220, the interrupt control unit 240 outputs “1” as the selection signal 141 to the multiplexer 150 and “1” as the control signal 142 to the program counter 110. 1 ”is output. At the same time, the program counter in the interrupt controller 240 starts operating. The program counter is the register 22 in the register 220.
2. The address 245 for selecting the instruction of the register 221 is output. The program counter 110 receives the control signal 142
The value is held by the value "1" of. The multiplexer 150 outputs the instruction 125 according to the value “1” of the selection signal 141.
To output. The value of the selection signal 141 is “0”
In the case of, the instruction 105 is selected. Instruction decoder 16
0 decodes the instruction 155, that is, the instruction corresponding to the interrupt request 130.

Here, the first instruction of interrupt processing is started without overhead. Interrupt control unit 2 for each instruction
The program counter in 40 is updated to register 220
The address of the instruction of the register 224 and the register 223 in the inside, and the address of the instruction of the register 226 and the register 225 in the register 220 are sequentially output.

Address decoder 22 in register 220
7 receives the address signal 245 and receives the multiplexer 228.
To select the corresponding instruction. Instruction decoder 160
Sequentially decodes the instruction 155 (the instruction 125 is selected by the multiplexer 150), whereby the interrupt processing is executed. After three instruction cycles, the interrupt control unit 240 detects the end of the interrupt program.
(The program counter is 3), the control signal 141 is set to "0", and the control signal 142 is set to "0" and output. The program counter 110 inputs "0" of the control signal 142 and starts updating the held access address, and the multiplexer 150 inputs "0" of the selection signal 141 to select the instruction 105. As a result, it is possible to automatically execute the interrupt program 3 instruction without branch instruction and automatically return to the original program.

[0037]

According to the present invention, in response to an interrupt request that can be processed with a few instructions by a slight change in hardware, the processing is executed without branching after acceptance of the interrupt and the original program is automatically executed after the instruction is executed. It is possible to provide an interrupt device that returns to the. Also, different interrupt processing can be realized by the same interrupt request by changing the instruction code stored in the storage means.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an interrupt processing device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a storage means in the same embodiment.

FIG. 3 is a configuration diagram of an interrupt processing device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a storage unit in the same embodiment.

[Explanation of symbols]

100 program memory 105, 125, 155 instruction 110 program counter 120-122, 220-222, 223-226 register 130 interrupt request signal 140, 240 interrupt control section 141, 142 control signal 150 multiplexer 160 instruction decoder 170 data bus 245 address 227 Address decoder 228 multiplexer

Claims (8)

[Claims] 1. A storage means connected to a data bus and readable / writable by a program, a program memory for storing the program, a first program counter for designating an access address of the program memory, and the program memory. A signal switching means connected to the storage means for selecting and outputting any one of the outputs, and a selection signal for outputting to the switching means in response to an interrupt request, and an update stop signal for the first program counter. An interrupt processing device comprising an interrupt control means for outputting and an instruction decoder connected to the switching means for decoding an instruction code of the output. 2. The interrupt control means has a second program counter therein, operates the second program counter in response to an interrupt request, counts a preset number of times, and then selects to the switching means. 2. The interrupt processing device according to claim 1, which has a function of stopping output of a signal and an update stop signal to the first program counter. 3. The interrupt processing device according to claim 2, wherein the interrupt control means has a function of outputting an address indicated by a second program counter. 4. The interrupt processing device according to claim 3, wherein the storage means has a function of outputting an instruction code stored according to an address output from the interrupt control means. 5. The interrupt processing device according to claim 4, wherein the interrupt control means has a function of outputting different addresses corresponding to a plurality of interrupt requests. 6. An interrupt processing method for changing control of a program by stopping updating of a program counter for instructing an access address of a program memory in response to an interrupt request and changing the selection of a switching means to a storage means side at the same time. 7. The interrupt processing according to claim 6, wherein in the processing method, the selection by the switching means is changed to the program memory side after the preset number of times the program is executed, and the update of the program counter is restarted. Method. 8. The interrupt processing method according to claim 7, wherein different processes are executed by the same interrupt request by changing a program stored in said storage means.