JPH0683986A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To easily select an interruption processing and to improve interruption processing speed by providing two registers and switching them at the time of interruption processing. CONSTITUTION:The single chip microcomputer consists of an instruction execution unit 1 containing registers 2, 3, CPU control register 4, 5, and inverter 6, interruption controller 7, OR circuit 8, AND circuit 9, 13, RAM 10, address generation circuit 11, inverter 12, instruction queue 14, bus control unit 15, cache memory 16, ant memory 17. Thus, many registers are prepared for an interruption source and the address of an address generation circuit 11 is stored at the generation of the next non-vector interruption during the non-vector interruption processing. At the end of the execution of the next non-vector interruption processing, the address stored in the address generation circuit 11 is returned to the address generation circuit and the former non-vector interrutpion processing is executed again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single chip microcomputer, and more particularly to a single chip microcomputer having an interrupt function.

[0002]

2. Description of the Related Art Conventionally, a single-chip microcomputer of this type has a register 2 as shown in FIG.
And instruction execution unit 1 including CPU control register 4
, Interrupt controller 7, instruction queue 14, bus control unit 15, cache memory 16
And a memory 17 are provided.

In FIG. 3, when an interrupt request is issued from the interrupt controller 7 via the bus 201, FIG.
As can be seen from the flowchart at the time of interrupt processing in (a), the interrupt controller 7 outputs the vector address corresponding to the interrupt to the instruction execution unit 1 via the internal bus 201 (step 31). Next, the vector address is read in the instruction execution unit 1 (step 32), the vector address is given to the bus control unit 15, and the data at the address indicated by the vector address is cached in the bus control unit 15. If it exists in the memory 16,
When the vector data is received from the sash memory 16 and the data does not exist in the cache memory 16, the bus control unit 15
Activates a bus cycle to receive vector data,
It is transmitted to the instruction execution unit 1 (step 33). In the instruction execution unit 1, after the current instruction is completed, the interrupt processing is started, and the program counter (PC) and the program status word (PSW) are saved in the stack area indicated by the value of the stack pointer (SP). (Step 34). The bus control unit 15 is connected to the program counter (PC).
The vector data received from the CPU is written, and the branch address is written to the bus control unit 15 (step 35). In the bus control unit 15, if the program of the branch address exists in the cache memory 16, the instruction code is read from the cache memory 15, and if it does not exist, a bus cycle is activated and the memory 17 reads it. The instruction code is fetched and the instruction code is read (step 36). The instruction queue 14 receives an instruction code from the bus control unit 15 via the bus 205 (step 3).
7) When the instruction execution unit 1 needs an instruction code, it gives an instruction queue output to the instruction execution unit 1 (steps 38 and 39). In addition, the instruction queue 14
If the instruction code is clogged, the instruction fetch stop signal is output to the bus control unit 15 and the instruction fetch of the bus control unit 15 is stopped. Bus control unit 15
In (1), if the address does not hit the smash memory 16, the bus cycle required for interrupt processing is activated. If the interrupt process is not a vector interrupt process but a simple process such as a transfer instruction and a logical operation, the microprocessor is programmed and the micro program is activated by an interrupt input to perform data transfer and operation. There is a method of speeding up interrupt processing by microprogram processing performed by processing and the like.

[0004]

In the above-mentioned conventional single-chip microcomputer having the interrupt processing function, in order to receive the instruction code after the interrupt request is received, the vector address of the vector address is passed through the bus control unit. When the vector code is read, the program counter and program status word are saved, and access is required by the bus control unit such as instruction code fetch. Therefore, even if the cache memory is built in, the cache does not hit. Has the drawback that it cannot increase the interrupt processing speed.

In the case where the interrupt process is a simple process, there is also a method of performing the interrupt process by selecting the microprogram process provided to the user incorporated in the microprogram. Has a drawback that the user cannot freely select the microprogram processing.

[0006]

A single-chip microcomputer of the present invention is a single-chip microcomputer having a built-in interrupt function, and an interrupt storing a plurality of instruction codes corresponding to an interrupt source executed during interrupt processing. It is formed by an instruction code storage means, an instruction code storage means for temporarily storing a plurality of instruction codes corresponding to normal operation, a register and a CPU control register, respectively, and corresponds to interrupt processing and normal operation. At least an instruction executing means including a functioning first and second combination circuit for receiving a predetermined instruction code and executing the instruction is provided, and reading the instruction code from the instruction code storage means at the time of the interrupt processing. And the instruction corresponding to the interrupt source is stored in the interrupt instruction code storage means. Together sequentially reading the code, the second combination circuit included in the instruction execution unit, the first
It is characterized by switching to the combination circuit of.

The interrupt instruction code storage means is
The RAM may be used, or the ROM may be used.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, an instruction execution unit 1 including registers 2 and 3, CPU control registers 4 and 5, and an inverter 6, an interrupt controller 7, an OR circuit 8, an AND circuit 9 and 1
3, an RAM 10, an address generation circuit 11, an inverter 12, an instruction queue 14, and a bus control circuit.
Unit 15, cache memory 16, and memory 17
And is configured.

In FIG. 1, in the bus control unit 15, at the request of the instruction execution unit 1,
Instruction fetch and data read / write processing are performed. In this case, if there is no data in the cache memory 16, the bus cycle is activated and the instruction code and data are read from the memory 17. The data read by the lotus control unit 15 is taken into the instruction execution unit 1 via the internal bus 202, and the instruction code is taken into the instruction queue 14 via the bus 205. Instruction execution unit 1 is bus 2
Via 04, it is connected to the instruction queue 14 and the output of the RAM 10 in which the instruction code at the time of non-vector interrupt processing is stored. The instruction queue read signal 102 output from the instruction execution unit 1 and the non-vector interrupt processing selection signal 10
The output of the inverter 12 to which 1 is input is the AND circuit 13
Since the non-vector interrupt processing selection signal 101 is “0” during normal instruction execution, when the instruction queue read signal 102 becomes “1”, the instruction code is read from the instruction queue 14. Further, at the time of non-vector interrupt processing, the instruction queue read signal 102 and the non-vector interrupt processing selection signal 101 are input, and the non-vector interrupt processing selection signal 101 is “1”. When the read signal 102 becomes "1", the instruction code at the time of non-vector interrupt processing is stored R
The instruction code is read from AM10.

Further, in the internal register of the instruction execution unit 1, the output of the inverter 6 is normally "1" during instruction execution and vector interrupt processing, whereby the register 2 and the CPU register 4 are selected, On the other hand, during non-vector interrupt processing, the non-vector interrupt selection signal 101 becomes “1”, and instead the register 3
And the CPU control register 5 is selected. Then, the instruction execution unit 1 writes to the mode register of the interrupt controller 7 via the bus 202 to set the interrupt processing mode. When the interrupt processing is in the vector interrupt processing mode, an interrupt request is output to the instruction execution unit 1 via the bus 201, and the vector code is output after the interrupt is accepted.

At the time of a vector interrupt, the non-vector interrupt processing selection signal 101 remains "0", and in the case of a non-vector interrupt without a vector interrupt, the non-vector interrupt processing selection signal 101 is "1". "It becomes. In the interrupt controller 7, an instruction code selection signal corresponding to an interrupt source is output to the bus 203 during writing to the RAM 10 and during non-vector interrupt processing. By the instruction code selection signal input via this bus 203,
RA is specified by the upper address of the RAM 10 and by an address signal input from the address generation circuit 11.
The lower address of M10 is designated. The address of the instruction for each interrupt source is specified via the bus 203,
Further, the address generation circuit 11 specifies the address in the instruction at each interrupt source. The address generation circuit 11 is initialized by the initialization signal 103 output from the interrupt controller 7 to indicate the start address of the instruction, and is output as an OR output of the write signal 104 and the read signal 105 output from the AND circuit 9. The read / write signal 105 of the instruction is incremented for each address to generate continuous write / read addresses of the instruction code, which are input to the RAM 10.

In the RAM 10, a write command code input via the data bus 202 via an address signal input via the bus 203 and an address signal input from the address generation circuit 11 is written. Written by signal 104. When the non-vector interrupt process is executed, the read signal 105 output from the AND circuit 9 outputs an instruction code to the bus 204 corresponding to the output of the instruction queue 14.

Next, the operation will be described. For the operation during normal instruction execution and vector interrupt,
Since it is exactly the same as the case of the above-mentioned conventional example, the description thereof will be omitted, and the operation of the non-vector interrupt processing without the newly added vector processing will be described.

First, RA at the time of execution of interrupt processing
The instruction code writing operation for M10 will be described. The write address output to the bus 203 is selected by the interrupt controller 7 (step 6).
1), initialization signal 103 for address generation circuit 11
Is output (step 62), and the start address of the instruction corresponding to the designated interrupt source is input to the address of the RAM 10. Next, the instruction execution unit 1 outputs the instruction code to be executed at the time of interruption to the internal bus 202 (step 63), and also outputs the write signal 104 to write one instruction code to the RAM 10 (step 64). ). After that, the count-up signal 106 to the address generation circuit 11 is output via the NAND circuit 8, and in the address generation circuit 11,
The write address of the next instruction code is generated (step 65).

In this manner, the instruction code data is sequentially given, the write signal 104 is output, and the instruction code at the time of non-vector interrupt processing is written (at the steps 63, 64, 65 and 66). At the end of the instruction, a return instruction from non-vector interrupt processing is written (due to repetition) (step 67). Similarly, the interrupt controller 7
The interrupt address output from is switched, and the instruction code corresponding to the source is written to each interrupt.
Then, the interrupt processing mode is switched to the non-vector interrupt processing without the vector interrupt.

Next, the operation during non-vector interrupt processing will be described. In FIG. 1, when the interrupt controller 7 outputs an interrupt request via the bus 201 and the instruction execution unit 1 accepts the interrupt request,
In the interrupt controller 7, when the interrupt request corresponds to the non-vector interrupt process, the non-vector process selection signal 101 is set to "1" as seen in the flowchart for the non-vector interrupt process in FIG. 4B. (Step 41), register 2 in instruction execution unit 1
And the CPU control register 4, register 3 and CP
It is switched to the U control register 5. Next, as the interrupt address corresponding to the interrupt source, the instruction code selection signal is output to the bus 203 (step 43), and the initialization signal 103 is output to the address generation circuit 11 (step 44) to correspond to the interrupt. The leading address of the interrupt to be output is output to the RAM 10.

After that, the process proceeds to the instruction processing execution routine from the RAM 10, and the instruction code is read from the RAM 10 by the instruction queue read signal 102 (step 4).
At the same time, the address generation circuit 11 is counted up and the next instruction code is selected (step 4).
6). Then, in the instruction execution unit 1, the read instruction code is executed (step 47), and if the execution instruction is not the interrupt return instruction, the RAM 1 is read again.
The instruction code is read from 0 to continue the execution of the instruction (by repeating steps 45, 46 and 47), and if the instruction is a return instruction, the process returns to the return process from the non-vector interrupt processing routine. (Step 4
8). In the return processing from the non-vector interrupt processing by the return instruction, the non-vector processing selection signal 101 is set to "0" (step 49), the register 3 and the CPU control register 5 in the instruction execution unit 1 are set to the register 2 and Returned to the CPU control register 4 (step 5
0), the instruction code is read from the instruction queue 14, and normal instruction execution is started again (step 51).

In this embodiment, since there is only one register used during non-vector interrupt processing, multiple interrupts during non-vector interrupts cannot be accepted. However, a large number of registers are prepared for the interrupt source, the address of the address generation circuit 11 is stored when the next non-vector interrupt is generated during the non-vector interrupt processing, and after the execution of the next non-vector interrupt processing is completed. By returning the address stored in the address generating circuit to the address generating circuit and executing the previous non-vector interrupt process again, it is possible to receive multiple interrupts of the non-vector interrupt process.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing this embodiment. As shown in FIG. 2, this embodiment uses registers 2 and 3, C
An instruction execution unit 1 including PU control registers 4 and 5, and an inverter 6, an interrupt controller 7, an address generation circuit 11, an inverter 12, AND circuits 13 and 19, an instruction queue 14, and a bus control unit. 15, a cache memory 16, and a memory 17 are provided.

As is clear from the comparison with FIG. 1, the first
In contrast to this embodiment, the RAM 10 for storing the instruction code at the time of interrupt processing is constituted by the mask ROM 18 in this embodiment. In the case of a mask ROM, the ROM code can be created in the same process as the user ROM. Therefore, in this embodiment,
Compared with the first embodiment, it is not necessary to execute writing to the RAM by executing an instruction, so that a RAM write signal and a data bus input write control circuit for writing data are not required at all. . That is, the operation in this embodiment is an operation in which the write operation to the RAM 10 in the above-described first embodiment is excluded. The other operations are similar to those of the first embodiment, and the description thereof will be omitted.

Compared to the first embodiment, this embodiment does not require the hardware required for writing, so that there is an effect that the chip area can be reduced, and the RAM writing There is an advantage that the required processing time becomes unnecessary and the initial setting time is shortened.

[0023]

As described above, according to the present invention, the instruction code storage means for storing a plurality of instruction codes corresponding to the interrupt sources executed at the time of the added interrupt processing, and the reading from the instruction queue at the time of the interrupt processing. And a means for reading an instruction code corresponding to an interrupt from the instruction code storage means and a means for switching the register at the time of the interrupt processing by adding an instruction code corresponding to the interrupt to the vector interrupt processing execution function. This makes it possible to select and execute interrupt processing that does not involve vector interrupt processing.
It is easy to select user programmable interrupt processing that executes instructions in multiple steps.
The response speed of real-time control that can be executed at high speed is improved, and the interrupt processing speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing a flowchart of interrupt processing and write processing.

[Explanation of symbols]

 1 instruction execution unit 2, 3 register 4, 5 CPU control register 6, 12 inverter 7 interrupt controller 8 OR circuit 9, 13, 19 AND circuit 10 RAM 11 address generation circuit 14 instruction queue 15 bus control unit 16 cache memory 17 memory 18 ROM

Claims (3)

[Claims] 1. A single chip with a built-in interrupt function.
In a microcomputer, an interrupt instruction code storage means for storing a plurality of instruction codes corresponding to an interrupt source executed during interrupt processing, and an instruction code storage means for temporarily storing a plurality of instruction codes corresponding to a normal operation, An instruction for receiving a predetermined instruction code and executing the instruction, including first and second combination circuits each formed by a register and a CPU control register and functioning in response to interrupt processing and normal operation At least during execution of the interrupt processing, the instruction code reading from the instruction code storage means is stopped, the instruction code corresponding to the interrupt source is sequentially read from the interrupt instruction code storage means, and Switching the second combination circuit included in the instruction execution means to the first combination circuit. A single-chip microcomputer characterized by and. 2. The interrupt instruction code storage means is RA
The single-chip microcomputer according to claim 1, wherein the single-chip microcomputer is constituted by M. 3. The interrupt instruction code storage means is RO
The single-chip microcomputer according to claim 1, wherein the single-chip microcomputer is constituted by M.