JP3097602B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus having a pipeline control function and having a dedicated function for debugging software.

[0002]

2. Description of the Related Art Recent microcomputers have a so-called RISC (Reduced Instruction Set Compiler) having a pipeline operation mechanism for increasing the operating frequency.
Many (uter) types have been developed. In general, R
Pipeline control in an ISC type processor is divided into five stages: instruction fetch, instruction decode, operand fetch, operation execution, and result storage.

A method of debugging software in a conventional microcomputer will be described. Usually, in order to debug software, the operation is stopped by a predetermined instruction in the program, the instruction address executed by the CPU so far is traced, the register contents in the CPU are dumped, and the memory contents are dumped. And so on.

FIG. 3 is a block diagram showing a configuration of a data processing device of a RISC type processor in a conventional example.
The data processing device shown in FIG. 3 includes an instruction fetch unit 100, an instruction decode unit 101, an operand fetch unit 102, and an arithmetic unit 10 which are units that execute five stages.
3 and the result storage unit 104 and the save registers 105 to 1
09, a pipeline control unit 110, a breakpoint register 111, a program counter 112, a program memory 115, and a save register 116. Here, the instruction fetch unit 100,
An instruction decoding unit 101, an operand fetch unit 102,
The arithmetic unit 103 and the result storage unit 104 each include:
The save registers 105 to 109 are connected. The pipeline control unit 110 includes a breakpoint register 1
11 and a program counter 112 are connected. The program counter 112 includes the save register 11
6 are connected. During normal instruction execution, the program counter 112 is incremented by one address. Further, control of the entire processing is performed by the pipeline control unit 11.
Perform at 0.

When debugging software, first, a breakpoint register 111 is set. The breakpoint register 111 is set by executing a normal I / O setting instruction. That is, when the instruction decoding unit 101 detects that the instruction is a write instruction to the breakpoint register 111, the operand fetch unit 102 generates write data, and the result storage unit 104
Through the pipeline control unit 110 to rewrite the contents of the breakpoint register 111. Thereafter, the pipeline control unit 110 compares, for each instruction, whether the program counter 112 matches the breakpoint register 111. If they match, a signal 200 instructing the save registers 105 to 109 to save the execution state of each stage 100 to 104 is activated.

As a result, the save register 105 contains
Information on the currently fetched instruction is saved from the instruction fetch unit 100. The save register 106 saves decode information of the immediately preceding instruction from the instruction decode unit 101. The save register 107 includes the operand fetch unit 1
The operand information of the instruction two before the 02 is saved.
In the save register 108, the operation information of the instruction three instructions before from the operation unit 103 is saved. In the save register 109,
The result storage information of the instruction four steps before is saved from the result storage unit 104. At the same time, the program counter 11
2 is stored in the save register 116.

In the program memory 115, the execution of the debug program is started by jumping to an address where a predetermined debug program is stored. The debug program executes a program for dumping the contents of registers and memory.

The return from the debug program is performed as follows. At the end of the debug program, a dedicated return instruction is programmed. When this instruction is executed, the pipeline control unit 110
To the units 100 to 104, and further saves the contents of the save register 116 to the program counter 1
Return to 12. This completely returns to the state before the execution of the debug program.

[0009]

The conventional debugging method described above has a drawback that the hardware scale of the save register for saving the state of each pipeline stage is very large, and the cost is increased. For example,
The save register 105 for fetching instructions has 32
Requires a register to store the bit instruction code.
The save register 106 for decoding an instruction requires a register for storing over 100 types of decoded control signals. The save register 107 needs to store three sets (first operand to third operand) of five pieces of address information for identifying a 32-bit register or an immediate value. The save register 108 requires two 32-bit operation inputs. Save register 109
Requires a 32-bit operation result. Thus, the CP executed by the subsequently executed debug program
In order to be able to return even if the internal state of U is broken, it was necessary to save the state of the pipeline.

[0010] Further, since these save registers are multiplexed with ordinary circuits, they serve as so-called critical paths that limit the operating frequency. For this reason, there is a disadvantage that the operating frequency is lower than that of a CPU without such a debug function.

Furthermore, since the debug program is mapped in the same space as the application program space, there is a drawback that software design has restrictions such as memory size and program link.

[0012] In view of the above, an object of the present invention is to provide a data processing apparatus that reduces costs and improves operating frequencies by reducing hardware, and simplifies software development procedures.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks, a data processing apparatus according to the present invention, when detecting a command to stop a program while executing the program instruction, issues a nop instruction instead of the program. When a command to execute and return the program is detected, execution of the program is resumed instead of the nop instruction.

The data processing apparatus according to the present invention is a data processing apparatus having a pipeline control mechanism, wherein first instruction fetch means (115) for fetching an instruction of a first program (application program); Detecting means (1) for detecting whether a preset stop condition for stopping the execution of the instruction of the first program (application program) is provided; and detecting means ( 1), a second instruction fetch means (4) for automatically fetching a nop instruction following a valid instruction of the first program (application program) to be executed, and a second program (debug) Third instruction fetch means (3) for fetching instructions of the program);
Instruction selecting means (115) for selecting an instruction to be fetched by any one of the first instruction fetching means (115), the second instruction fetching means (4), and the third instruction fetching means (3) Wherein the instruction selecting means (2) selects the first instruction fetch means (115) and executes the first program (application program),
When the detecting means (1) determines that the stop condition has been satisfied, the instruction selecting means (2) selects the second instruction fetch means (4) and determines whether the second instruction fetch means (4) has been satisfied. The nop instruction is fetched after the valid instruction, and after the execution of the valid instruction is completed, the instruction selecting means (2) selects the third instruction fetch means (3) and executes the second program When the second program (debug program) is being executed and the second program (debug program) is being executed, the instruction selecting means (2) includes the second instruction fetching means (4) and the third instruction fetching means. Means (3) are alternately selected, and when a predetermined return instruction is executed in the second program (debug program), the instruction selection means (2) causes the first instruction fetch means (115) to select.

The data processing apparatus of the present invention is characterized in that
The instruction fetch means (3) can include input means (5) for externally inputting the second program (debug program) via a serial interface.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment] A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a data processing device according to the embodiment.

The data processing apparatus shown in FIG. 1 has a pipeline control unit 1, a multiplexer 2, a debug program memory 3, a nop insertion unit 4, an instruction fetch unit 100 which is a unit for executing each pipeline, Instruction decoding unit 101, operand fetch unit 102, operation unit 1
03, a result storage unit 104, a breakpoint register 111, a program counter 112, a program memory 115, and a save register 116. Here, the instruction fetch unit 100, the instruction decode unit 101, the operand fetch unit 102, the operation unit 103, and the result storage unit 104 are connected to the pipeline control unit 1. Also, the program counter 11
2 is connected to a save register 116.

In such a configuration, each unit 10
Normal operations of 0 to 104, the breakpoint register 111 and the program counter 112 are the same as those described in the related art. The main difference is that there are no save registers 105 to 109, each unit 100 to 104 is directly connected to the pipeline control unit 1, and the multiplexer 2 for fetching an instruction includes a program memory 115, a nop insertion unit 4 That is, the debug program memory 3 is input and the output is input to the instruction fetch unit 100.

When debugging software, first, the breakpoint register 111 is set as described in the background art. Thereafter, the pipeline control unit 1 compares each instruction whether the contents of the program counter 112 and the contents of the breakpoint register 111 match. If they match, the selection signal 20
Is activated, and the multiplexer 2 selects the output of the nop insertion unit 4. As described above, since only the nop instruction is inserted after the instruction specified by the breakpoint, all instructions before that are executed as usual. Therefore, after a minimum of 5 clocks, the execution of the instructions including the instruction specified by the breakpoint is completed. Even if a so-called pipeline hazard in which the operation of the pipeline is disturbed and the processing time is prolonged during this time, the nop instruction is continuously fetched until the end thereof.

When the pipeline controller 1 confirms that all instructions before the breakpoint have been executed, it switches the selection signal 20 to the multiplexer 2.
Selects the output of the debug program memory 3. The debug program memory 3 uses a lower speed than the program memory 115 in order to reduce the cost. First
In the embodiment, the access time of the debug program memory 3 is configured to be 1/2 of the access time of the program memory 115.

By controlling the selection signal 20 in this manner, the multiplexer 2 selects the output of the program memory 115 during normal program execution, and when debugging, executes the nop insertion section until the instruction before the breakpoint ends. Select the nop instruction that is the output of 4
After all instructions before the breakpoint have been completed, the output of the debug program memory 3 is selected.
The output of the op insertion unit 4 and the output of the debug program memory 3 are alternately selected. As a result, the application program can be set to no without stopping the pipeline control during debugging.
The debug program can be executed while executing the p instruction.

At the end of the debug program, a dedicated return instruction is executed at the end of the debug program so as to fetch from the instruction following the break pointer. As a result, the contents of the save register 116 are stored in the program counter 1
12, the multiplexer 2 is connected to the program memory 11
5 is selected and output.

In the debug program of the present invention, consideration is given to software so as not to change the so-called internal state. This is a limitation in designing a debug program, but since the debug program itself is simple and does not depend on application programs, once the design is completed, it should be used for general purposes. Can be. Factors that change the internal state include the contents of registers. When dumping the contents of the memory, indirect addressing must be performed using registers. However, this value is saved in the debug program memory 3 at the beginning of the debug program, and the saved contents are written immediately before returning. return.

Further, depending on the type of RISC processor, if the instruction set as a breakpoint is a branch instruction, there is one designed to always execute the immediately following instruction. In this case, the limitation is that a breakpoint cannot be set at the branch instruction.
There is no major problem in use.

In the first embodiment, the debug program memory 3 is set in a space independent of the program memory 115. The purpose of this is to separate the debug program from the application program, thereby avoiding the size limitation in the application program design, and increasing the development efficiency by eliminating the link between the two programs. Naturally, by mapping the debug program memory 3 in the same memory space as the program memory 115, it is possible and easy to physically combine both memories. In this case, the multiplexer 2
Is changed from three inputs to two inputs, but it is obvious that it can be easily realized.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIG. FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a data processing device according to the embodiment.

The configuration of the data processing device shown in FIG. 2 is almost the same as the configuration of the data processing device according to the first embodiment shown in FIG. The difference is that a serial interface 5 is provided instead of the debug program memory 3. The serial interface 5 inputs the output to the multiplexer 2, performs input / output with the pipeline control unit 1 using the serial control signal 10 and the reception completion signal 11, and connects the output of the result storage unit 104 to the data bus 30. You are typing through. As described above, in the second embodiment, the debug program is fetched via the serial interface 5 without using the debug program memory 3.

In such a configuration, when the pipeline control unit 1 detects a breakpoint, the selection signal 20
And the multiplexer 2 selects the output of the nop insertion unit 4. At the same time, the pipeline control unit 1 activates the serial control signal 10 to start the operation of the serial interface 5. The serial interface 5 communicates with an external host computer (not shown) by a start-stop synchronization procedure, and receives a debug program prepared in advance one instruction at a time. When the reception of one command is completed, the reception completion signal 11 is activated. In response to this, the pipeline control unit 1 controls the selection signal 20 so that the multiplexer 2 selects the output of the serial interface 5 only for one clock.

In this way, the debug program is executed one instruction at a time. The dump of the register and the memory itself is performed as follows. A transmission register (not shown) is provided inside the serial interface 5, and stores the dumped contents from the result storage unit 104 via the data bus 30 in the transmission register. This storage itself is executed in the debug program. Switching between reception and transmission is all controlled by the host computer. When the dump data is collected with the progress of the debug program, transmission is requested to the serial interface 5 and the dump data is collected to the host computer by serial communication.

At the end of the debug program, a dedicated return instruction is programmed. By executing this, the contents of the save register 116 are stored in the program counter 1
12, the multiplexer 2 is connected to the program memory 11
Select 5.

[0032]

As described above, according to the present invention, when a debug program is executed by inserting a nop instruction without stopping the pipeline operation when a breakpoint is detected, the state of the pipeline can be changed. There is an effect that it is not necessary to add hardware for saving, and hardware added for executing the debug program can be reduced. In the prior art, five save registers require a register of at least 250 bits in total and a corresponding selection circuit (approximately 5k gates), whereas the present invention does not require the entire hardware (approximately 50k). Gate) can be reduced by about 10%. Although the longest number of gate stages in each pipeline is about 20, the reduction of one gate of the selection circuit for restoring the save register has the effect of improving the operating frequency by about 5%. Have.

In the first embodiment, the program memory and the debug program memory are independently provided, and the maximum allowable size of the application program is substantially reduced by mapping the debug program in a space independent of the application program space. This has the effect of expanding to. In general, the size of a debug program is required to be about 100 Kbytes. Therefore, when the application program is about 1 Mbyte, about 10% can be effectively used. In addition, there is no need to link with a debug program when creating an application program, which has the effect of simplifying the software development procedure.

In the second embodiment, the use of the serial interface instead of the debug program memory has the effect of greatly reducing the number of terminals between the RISC processor and the host computer.

Here, in the first embodiment, it is advantageous that the execution speed is as fast as usual even at the time of debugging, but the execution speed is 32 bits, the 32-bit data bus, the 32-bit address bus, and the control signal. And so on must be provided as terminals, which is expensive. R all debug programs
If the chip can be built in the ISC processor, there is no problem with the number of terminals, but the chip size increases, which causes a cost increase. On the other hand, in the second embodiment, the execution speed of the debug program is lower than that of the first embodiment. Does not pose a major problem, and has a great advantage that the circuit scale of the serial interface is small and that the cost can be significantly reduced by reducing the number of terminals.

As described above, the present invention has an effect that the cost can be reduced and the operating frequency can be improved by reducing the hardware, and the software development procedure can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a data processing device of a RISC type processor in a conventional example.

[Explanation of symbols]

 1, 110 Pipeline control unit 2 Multiplexer 3 Debug program memory 4 Nop insertion unit 5 Serial interface 100 Instruction fetch unit 101 Instruction decode unit 102 Operand fetch unit 103 Operation unit 104 Result storage unit 105 to 109, 116 Save register 111 Breakpoint register 112 program counter 115 program memory

Claims (3)

(57) [Claims] 1. A data processor having a pipeline control mechanism.
In management apparatus, an instruction fetch unit, an instruction decode unit, an operand fetch
Stages of operation in the storage unit, operation unit, and result storage unit
A pipeline control unit that controls
Program memory to store and program memory for debugging
Debug program memory for storing
A nop insertion part, the program memory, and the debug
Of each output of the program memory or the nop insertion unit,
Select one of them and output to the instruction fetch unit.
Break on the multiplexor and the execution program
A breakpoint register to hold points
A program counter and a save register .
When the value matches, the save register stores the program
While holding the counter value, the pipeline system
The control unit includes the instruction specified by the breakpoint.
The multiplexer is a nop instruction until the instruction is completed.
Is output, and the instruction specified by the breakpoint is included.
After the completion of the instruction, the multiplexer
Control to output a program for use
That, the data processing device. 2. A data processing device having a pipeline control mechanism, wherein: first instruction fetch means for fetching an instruction of a first program; and a preset instruction fetch means for stopping execution of the instruction of the first program. Detecting means for detecting whether or not the stopping condition has been satisfied; and when the detecting means determines that the stopping condition has been satisfied, a nop instruction is automatically provided following a valid instruction of the first program to be executed. Instruction fetch means for fetching an instruction of the second program, third instruction fetch means for fetching an instruction of the second program, the first instruction fetch means, the second instruction fetch means, and the third instruction fetch Means for selecting an instruction to be fetched by any one of the first means and the first means for selecting the first instruction fetch means. If the detecting means determines that the stop condition is satisfied during execution of the first program, the instruction selecting means selects the second instruction fetch means and the stop condition is satisfied. Fetching the nop instruction after the valid instruction at the time, and after the execution of the valid instruction is completed, the instruction selecting means selects the third instruction fetch means and executes the second program. When the second program is being executed, the instruction selecting means alternately selects the second instruction fetch means and the third instruction fetch means, and a predetermined return in the second program is performed. A data processing device , wherein when an instruction is executed, the instruction selecting means selects the first instruction fetch means . 3. The data processing apparatus according to claim 2, wherein said third instruction fetch means includes an input means for externally inputting said second program via a serial interface.