JPS6230452B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device controlled by a microprogram, and particularly to a waiting time control method.

In recent years, microprocessors with a built-in memory device on a single silicon substrate have appeared, and have come to be used for a variety of purposes. In such a so-called one-chip microprocessor, when introducing the output terminal to the input terminal via a key switch, etc., the switching speed due to the load on the output terminal is taken into consideration, and the output signal is derived from the output terminal and then the appropriate It is necessary to introduce the input signal to the microprocessor from the input terminal after a certain period of time has elapsed. Alternatively, when using the output terminal to drive a device with a slow operating speed, such as a mechanical device, it is necessary to derive the output signal for a time commensurate with the operating speed. For this reason, in conventional microprocessors, no-operation instructions (hereinafter referred to as
Execute an appropriate number of NOP instructions (abbreviated as NOP instructions),
A method of controlling time using a timer counter is known. However, such a method may result in an increase in program memory or
It required a timer/counter, which increased the hardware, and when it was applied to a large-scale integrated circuit (hereinafter referred to as LSI), it had the disadvantage of increasing the chip area.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an inexpensive information processing device that can perform time control without increasing program memory or using a timer/counter.

In FIG. 1 showing a conventional information processing device,
10 is a lead that stores the micro program.
Only memory (hereinafter abbreviated as ROM)
It has N address spaces. 11 is ROM10
12 is a stack register that saves program counter 11;
1 and stack register 12 have n bits of output information and can specify 2 ⁿ addresses. 1
3 receives the output of the program counter 11
An address decoder converts it into an address selection signal for the ROM 10, and 14 is a control device (hereinafter abbreviated as CPU) that receives the output of the ROM 10 and performs various arithmetic processing, generation of control signals, etc. 15 is CPU1
This is a timer/counter that controls time. I11 and O10 are an input terminal and an output terminal, respectively, and 16 is a switch added to the outside of the information processing device. Now output terminal O10
When the output signal is derived from the input terminal I11 via the switch 16, the input signal is input after an appropriate time has elapsed after the execution of the output command, taking into consideration the delay in switching time due to the load capacitance of the output terminal O10, etc. instructions need to be executed. FIG. 2a is a flowchart showing the above-mentioned processing procedure. After the output command is executed, a waiting time is inserted by executing the NOP command, and then the input command is executed. Here, if the NOP instruction execution time is t _o and the number of executions is m ₁ , the waiting time tw is t _w = t _o × m ₁ , but if the waiting time _tw is large and the NOP instruction execution time is small, the The number of executions m ₁ increases, ROM usage becomes very inefficient, and ROM
This results in an increase in capacity. For this reason, there is a method of controlling the waiting time by providing a timer/counter. The flowchart is shown in FIG. 2b. In this case, if you set the timer counter's count number appropriately,
Although the efficiency of ROM usage does not deteriorate so much, a timer counter is required, resulting in an increase in hardware. Therefore, when applied to LSI, it will lead to an increase in ROM capacity and other hardware.
The drawback was that it hindered LSI cost reduction.

The present invention has a memory to which N addresses are allocated, and an address generation circuit connected to this memory and capable of counting up to M addresses larger than the N, and after executing a predetermined instruction, the next In an information processing device that executes a process that requires a waiting time before executing an instruction, an address that is not allocated to the memory after executing the predetermined instruction is set in the address generation circuit, and counting is started from the address. When a specific address is reached, the execution of the next instruction is started, and while the addresses not allocated in the memory are being counted, the output of the memory is fixed to a specific instruction code. The present invention is characterized in that the waiting time is the above-mentioned waiting time.

FIG. 3 shows an embodiment of this invention, and 30 is
It has N addresses (for example, 1536) in ROM. 31 is a program counter that specifies the address of the ROM 30; 32 is a stack register that saves the program counter 31; the program counter 31 and the stack register 32 each have n bits of output information;
You can specify ⁿ addresses, but this is ROM30
is larger than the address N it has (for example, n=11
The address that can be specified is 2048). 33 is an address decoder, 34 is a CPU, and 35 is output when a subroutine call instruction is executed, and the contents of the program counter 31 are stored in the stack register 32.
This is a control signal for saving to. 36 is output when a subroutine return instruction is executed and stores the contents of the stack register 32 in the program counter 31.
37 is a signal that is output when the contents of the program counter 31 specify address 2047. Together with the control signal 36,
This becomes an input signal to the OR gate 38. Therefore signal 3
If 7 is output, the operation is similar to that of a subroutine return instruction. Figure 4 is Figure 3 ROM
30 and an address decoder 33, 40 is a ROM, 43 is an address decoder,
P1 to P11 are output signals from the program counter, and R0 to Rn are outputs from the ROM 40. Also a ₀
~a ₁₅₃₅ and a ₂₀₄₇ are the outputs of the address decoder 43, and 47 is an inverter.

Here, the program counter outputs P1 to P11
When specifying an address larger than address 1536, the outputs _a0 to _a1535 of the address decoder 43 are all unselected, and the ROM outputs R0 to Rn are all -V.
(logical 0) and NOP instruction code (normally all 0)
NOP).

Now, when using the output terminal O30 in Figure 3 to drive a mechanical device (not shown) with a slow operating speed, it is necessary to output an appropriate amount of time after executing the output ON command depending on the operating speed. be. Figure 5 is a flowchart showing the above-mentioned processing procedure. After executing the output ON command, if the program counter is set to a non-existing address in the program memory (address larger than address 1535) by a subroutine call command, the RON output will be NOP. The command is output. The program counter counts sequentially, executes NOP instructions sequentially, and reaches the maximum address (address 2047). At the maximum address (address 2047), the program counter performs the same operation as a subroutine return instruction.
Address next to call instruction execution address (output
OFF instruction execution address) and output is OFF.
Execute commands. As is clear from the above explanation,
Output time does not exist in program memory
Depending on which address from address 1536 to address 2047 is called, up to 512 NOP instruction execution times can be obtained. Moreover, in order to obtain more time, it is sufficient to execute the subroutine call instruction as many times as necessary. Figure 6 shows the address and
61 is a program memory area, and 62 is an area where no program memory exists. FIG. 7 is an address map of another embodiment of this invention, and 71 and 73 are program addresses.
This is a memory area, and 72 is an area where no program memory exists. Here, if you program a subroutine return instruction at address 1280 and call addresses from 768 to 1279 with a subroutine call instruction, no extra hardware is required and the same process as in the previous embodiment can be performed. Effects can be obtained.

As is clear from the above explanation, according to the present invention, in order to perform time control, the program memory is not wasted and special counters such as timers and counters are not required. This makes it possible to provide an extremely effective and highly versatile information processing device, especially for LSI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional information processing device, FIG. 2 is a flowchart for explaining FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram for explaining a part of FIG. 3, FIG. 5 is a flowchart for explaining FIGS. 3 and 4, FIG. 6 is an address map of an embodiment of the present invention, and FIG. is an address map of another embodiment of this invention. 10, 30, 40...program memory, 1
1, 31...Program counter, 12, 32
...Stack register, 13, 33, 43...
Address decoder, 14, 34...control device,
15...Timer counter, 16...Switch,
35, 36... Control signal, 37... Maximum address output, 38... OR gate, 47... Inverter, 61, 71, 73... Program memory area, 62, 72... Area that does not exist in the program memory.

Claims (1)

[Claims] 1 comprises a memory to which N addresses are assigned, and an address generation circuit connected to this memory and capable of counting up to M addresses larger than the N,
In an information processing device that executes processing that requires waiting time after execution of a predetermined instruction until execution of the next instruction,
After the execution of the predetermined instruction, an address that is not allocated in the memory is set in the address generation circuit, and when counting starts from the address and reaches a specific address, execution of the next instruction is started, and the memory An information processing device characterized in that while counting addresses that are not allocated to the memory, the output of the memory is fixed to a specific instruction code, thereby making this time the waiting time.