JPH08305564A - Microcomputer - Google Patents

Abstract

PURPOSE: To provide the microcomputer in which a transition time to a program processing based on an interrupt request can be reduced. CONSTITUTION: Data subject to be operated stored in a stack memory 10 are directly fed to one input of an arithmetic logic unit 13 and other arithmetic data latched by a latch circuit 11 are directly fed to the other input of the arithmetic logic unit 13 and an arithmetic output of the arithmetic logic unit 13 is stored in a register 14. Thus, even on the occurrence of an interruption request, only the content of the register 14 has only to be saved tentatively in th stack memory 10 and the time to be transited to the interrupt processing can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer configuration suitable for efficiently executing interrupt processing.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a configuration of a conventional microcomputer. In FIG. 2, (1) is a ROM, and a plurality of program data DATA for controlling the operation of the microcomputer are stored in advance at a plurality of addresses allocated to the storage area of the ROM (1). Is. Reference numeral (2) is a control circuit, which outputs address data ADD for accessing the address of the ROM (1) corresponding to each case, and is read from the address of the ROM (1) corresponding to the address data ADD. The program data DATA is fetched and decoded, and the operation of the microcomputer is controlled based on the decoding result. (3) and (4) are n-bit registers,
The control output of the control circuit (2) controls the data holding operation. For example, it is assumed that the register (3) and the register (4) hold n-bit data of the counters CTR1 and CTR2, each of which has a predetermined count value, via the data bus (5). The data set in the registers (3) and (4) is the counter C.
Not limited to the count values of TR1 and CTR2, but two types of n-bit data to be operated are input ports (not shown)
Via the computer to the inside of the microcomputer,
The n-bit data of a kind may be held in the registers (3) and (4) via the data bus (5), that is, any data can be set in the registers (3) and (4). Even the target. (6) is an arithmetic logic unit, which performs a predetermined logical operation (addition, subtraction, etc.) on each n-bit data held in the registers (3) and (4),
The n-bit data obtained as a result is held in one register (3) again.

The microcomputer is generally constructed as described above. Here, if an interrupt request occurs due to some factor during the execution of the main program for performing a logical operation on the contents of the registers (3) and (4), Instead of executing the main program, a subroutine program based on the interrupt request must be executed. Therefore, it is necessary to suspend the processing of the main program until it is executed, and temporarily save the processing data based on the main program until the subroutine program ends. Specifically, a stack memory (7) is provided, and when the interrupt request occurs, the stack memory (7) is controlled by the control signal of the control circuit (2), and the stack area STACK1 of the stack memory (7) is controlled. In STACK2 and STACK2, the values of the registers (3) and (4) at the time of interruption of the main program are temporarily saved via the data bus (5). Thus, the registers (3) (4) and the arithmetic logic unit (6)
Subroutine processing can be executed using. The subroutine processing is executed by the control circuit (2) accessing the address of the ROM (1) specified by the interrupt request, that is, jumping from the address at the time of executing the main program to the address at which the subroutine program processing is performed. .

[0004]

However, it is necessary to temporarily save the contents of both the registers (3) and (4) in the stack area of the stack memory (7) at the time of transition from the main program to the subroutine program based on the interrupt request. Therefore, there is a problem that it takes a long time to temporarily save, and as a result, the interrupt processing time becomes long.

Therefore, an object of the present invention is to provide a microcomputer capable of shortening the transition time to program processing based on an interrupt request.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that a micro-processor for performing a predetermined operation on two operand data according to a program instruction. In the computer, the above 2
A temporary save memory where two operands are stacked,
A latch circuit for latching one of the operated data previously read from the temporary save memory, and one of the operated data held in the latch circuit is applied to one input and the other input is applied to the other input. An arithmetic logic unit to which the other of the operand data read from the temporary save memory is applied and which performs a predetermined arithmetic operation on both operand data; and a register for holding the arithmetic result of the arithmetic logic unit, When an interrupt request is generated, only the contents held in the register are temporarily saved in the temporary save memory, and the program processing based on the interrupt request can be executed.

[0007]

According to the present invention, one input of the operation logic unit held in the temporary save memory is applied to one input of the operation logic unit, and the other input of the operation logic unit is held in the latch circuit. The other processed data is applied and the operation output of the operation logic unit is held in the register. Therefore, even if an interrupt request occurs, only the contents of the register need only be temporarily saved in the temporary save memory, and the time required to shift to interrupt processing can be shortened.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing the configuration of the microcomputer of the present invention. In FIG. 1, (8) is a ROM (memory) in which a plurality of program instructions for operating the microcomputer in a main routine or a subroutine are stored. Reference numeral (9) is a control circuit. When the address data ADD is output from the control circuit (9) between the ROM (8) and the control circuit (9), the corresponding address of the ROM (8) is accessed. , The program data DATA read from the corresponding address of the ROM (9) is decoded by the control circuit (9), and the operation of the microcomputer is controlled based on the decoding result. Reference numeral (10) is a stack memory (temporary save memory), which has a function of holding two types of processed data to be operated by an operation logic unit described later in the stack areas STACK1 and STACK2, respectively. The stack memory (10) has a function of temporarily saving the address information immediately after the main program is interrupted, whose temporary saving operation is controlled by the control output of the control circuit (9). There is. This address information is taken into the control circuit (2) side again when returning from the subroutine to the main program.
Reference numeral (11) is an n-bit configuration latch circuit, which latches one of the operand data previously read from the stack area STACK2 of the stack memory (10) so as to be operated by an arithmetic logic unit described later. is there.

Here, in the stack areas STACK1 and STACK2 of the stack memory (10), n of the counters CTR1 and CTR2 each having a predetermined count value.
Bit data shall be held via the data bus (12). The data held in both stack areas is not limited to the count values of the counters CTR1 and CTR2, and two types of n-bit data to be operated are fetched into the microcomputer via an input port (not shown). , The two types of n-bit data are transferred to the data bus (1
It may be held in both stack areas via 2),
That is, any data can be used as long as it can save to both stack areas.

(13) is the above-mentioned arithmetic logic unit, one input of which is directly connected to the output of the latch circuit (11) and the other input of which is directly connected to the stack memory (10). Then, the arithmetic logic unit (13) performs a predetermined arithmetic operation on both operand data. (1
Reference numeral 4) is a register having an n-bit configuration, which holds an n-bit operation result (addition, subtraction, etc.) performed by the operation logic unit (13) on both operand data.

In the microcomputer configured as described above, an interrupt is caused by some factor during execution of the main program, especially during execution of a program for performing arithmetic processing on two types of operand data in the arithmetic logic unit (13). If a request occurs, the operation result is held 1
Only the values of the registers (14) are stored in the stack memory (1
0), the main program is temporarily interrupted, and execution of subroutine processing based on an interrupt request can be performed.

Even if the subroutine processing based on the interrupt request is repeated many times, only the value of the register (14) needs to be temporarily saved in the stack memory (10), and each subroutine processing is different from the conventional one. It can run fast.

[0013]

According to the present invention, even if an interrupt request occurs during execution of a predetermined program, only the value of one register holding the operation result of the operation logic unit is saved in the temporary save memory. This is sufficient, and there is an advantage that the transition time to the program processing based on the interrupt request can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a microcomputer of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional microcomputer.

[Explanation of symbols]

 (10) Stack memory (13) Arithmetic logic unit (14) Register

Claims (2)

[Claims] 1. A microcomputer for performing a predetermined operation on two operand data in accordance with a program instruction, wherein a temporary save memory in which the two operand data are stacked, and one of the temporary save memories that have been previously read from the temporary save memory. And a latch circuit for latching the operated data, and one of the operated data held in the latch circuit is applied to one input and the other input read from the temporary save memory to the other input. An arithmetic logic unit that receives the operation data and applies a predetermined operation to both the operation data and a register that holds the operation result of the operation logic unit are provided. Only the contents are temporarily saved in the temporary save memory, and the program processing based on the interrupt request can be executed. Micro-computer which is characterized. 2. A control circuit for accessing a memory storing a program command and decoding the program command read from the memory, wherein the control circuit and the temporary save memory are based on a decoding result of the program command. The microcomputer according to claim 1, wherein data can be exchanged between them.