JPH036758A - Microprocessor - Google Patents

Abstract

PURPOSE:To easily switch the external devices with use of a mode switch signal even in a data processing system including a high speed bus by stopping the bus cycle when a mode is switched with the mode switch signal. CONSTITUTION:A microprocessor 7 switches its operation mode with a mode switch signal DBGACK and stops the bus cycle via a bus control means when the accesses are given to the external devices 8 and 9. Thus the microprocessor 7 assures no execution of the bus access and at the same time changes the mode switch signal to switch the operation mode. Thus the mode switch signal is changed in the timing where no execution of accesses is assured to both devices 8 and 9. Thus it is possible to easily switch the devices 8 and 9 with a mode switch signal even in a system having a high speed bus cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor having a plurality of operating modes, and more specifically to a microprocessor that switches its external devices using a mode signal.

[Conventional technology]

Figure 4 shows National Semiconductor's [5eries]
32000 DatabookJ, PP, 2-21
FIG. 2 is a system connection diagram of the conventional microprocessor shown in FIG.

In the figure, 21 is a CPU (microprocessor), and the cPU 21 converts a logical address into a physical address of a memory (not shown) and sends access information via a bus 23 to a memory management unit (hereinafter referred to as MMU) 22 that protects the memory. A mode signal U that provides a logical address and indicates whether the CPU 21 is operating in user mode or supervisor mode.
/Give evening.

Here, the user mode is a mode in which a user's application is operated, and the supervisor mode is a mode in which a system such as O8 is operated.

The mode signal U/S is output as the value of the bit of the status register (not shown) indicating the processor status of the CPU 21. When the mode signal U/S is at "H" level, it is user mode, and when it is at "L" level, it is output as the user mode. Indicates that it is operating in supervisor mode.

Next, the operation of a conventional microprocessor will be explained.

CPt 121 provides access information to MMU 22.

In response to this, the MMLI 22 not only converts the logical address to a physical address but also performs memory protection to protect the memory area according to the mode. In other words, M? III 22 receives the mode signal U/(, performs memory protection using the protection level set at that time and the state of the mode signal U, and protects the protected G'S jJ area on the memory determined according to the mode. Control to prevent access.

FIG. 5 is a timing chart showing the relationship between the change timing of the mode signal υ and bus access from the CPU. In this CPII 21, at least the CPU 21
The mode signal IJ/S is changed in two cycles in synchronization with the clock immediately before accessing the memory by the bus cycle, that is, immediately before outputting the next logical address to the bus. Then, the mode signal U is made stable at the timing shown in 8 before the CPU 21 accesses the outside, and the memory is accessed after the mode has been reliably switched. We ensure that protection is in place.

[Problem to be solved by the invention]

In the conventional microprocessor sensor, the operating mode is clearly indicated to the outside of the CPU by means of a mode signal, and the memory is accessed after the mode signal is stabilized, so that memory protection can be realized by hardware. However, C.P.
If the performance of U and its peripheral devices improves, the clock speed becomes faster, and the bus cycle period becomes shorter, the absolute time from the previous clock to the start of the next bus cycle will shorten, and the mode signal will change and stabilize. There is a risk that a bus cycle may be started before the other time.

This invention was made in consideration of the above circumstances, and by stopping the bus cycle to prohibit bus access while the mode signal is changing, the bus cycle is started after the mode signal stabilizes. An object of the present invention is to provide a microprocessor sensor that can easily switch external devices using a mode signal in a system with a high-speed bus cycle.

[Means to solve the problem]

The microprocessor according to the present invention switches the operating mode using the mode switching signal, and when accessing an external device, stops the bus cycle using the bus control means to ensure that no bus access is performed, and changes the mode switching signal during that time. The operation mode can be changed by changing the operation mode.

[Effect]

In this invention, the mode switching signal changes at a timing when it is guaranteed that no access is made to the external device, so even in a system with a high-speed bus cycle, the external device can be easily switched using the mode switching signal. .

〔Example〕

The present invention will be explained below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the vibe line of a microprocessor according to the present invention. During debugging, this microprocessor operates in a debug mode (hereinafter referred to as DBG mode) and a debug response mode (hereinafter referred to as DBGAC mode). The DBG mode is a mode for performing normal debug processing, and the DBGACK mode is a mode for debugging by performing data processing as exception processing. In the figure, 1 is an instruction fetch stage (hereinafter referred to as IF stage) that issues an access request to an external bus interface unit (hereinafter referred to as bus I/F unit) 6 to be described later and fetches an instruction code from memory; is the instruction decode stage (hereinafter referred to as D stage) 2 which decodes the instruction code, the operand address calculation stage (hereinafter referred to as A stage) 3 which calculates the execution address of the operand specified in the decoded instruction code, and the operand from memory. It is connected via an operand fetch stage (hereinafter referred to as F stage) 4 that fetches an instruction to an instruction execution stage (hereinafter referred to as E stage) 5 that executes an operation specified in an instruction code on an operand. Further, a bus INF unit 6, which is an interface with external devices, is connected to the IP data 1, A stage 3, F stage 4, and E stage 5.

IF stage 1 independently issues an access request to bus I/F section 6, fetches the instruction code from memory, and
Output to stage 2. D stage 2 is IP stage 1
It decodes the instruction code output from the A stage 3 and outputs the decode result to the A stage 3. A stage 3 calculates the execution address of the operand specified in the instruction code, issues an access request to the bus I/F section 6 if necessary, performs indirect address reference, and sends the calculated operand address to F stage 4. Output. The F stage 4 issues an access request to the bus I/F section 6 in accordance with the operand address input from the A stage 3, and fetches the operand from the memory via the external bus. The fetched operand is output to E stage 5. E stage 5 is F
The operation specified in the instruction code is executed on the operand output from stage 4. Furthermore, if necessary, an access request is issued to the bus I/F section 6, and the result of the calculation is stored in the memory. If there is no access request from the A, F, or B stages, the bus I/F unit G performs a pre-fetch of an instruction in response to an access request from the F stage 1.

Also, is there a mode identification signal from E stage 5 that identifies whether it is DBG mode or DBGACK mode? IS is output to the bus I/F section 6. Mode identification signal? IS is at the "H" level in the DBG mode, and is at the "L" level in the DBGA (J mode).Moreover, the mode switching signal D[1GACK is sent from the bus I/P section 6 to an external device (not shown).
Output.

This microprocessor normally operates in the DBG mode, and the mode switching signal DBGACK is output at "L" level. The transition from the DBG mode to the DBGACK mode is performed in the E stage 5. After the instruction being executed is completed, an access request is issued from the E stage 5 to the bus I/F section 6, and the "L" level is output to the mode identification signal MS. , followed by an access cancellation request.

The bus I/F unit 6 does not access the external bus for a period of time equal to the minimum bus cycle due to the access request and cancellation request from the E stage 5, and changes the mode switching signal DBGACK to the "L" level at the point of two cycles of that time. let

When DBGAC finishes processing in the mode, an access request is issued again from the E stage, and the mode identification signal becomes 1H.
Change in level. Subsequently, an access cancellation request is issued, and the bus I/F unit 6 does not access the external bus for a time equal to the minimum bus cycle due to the access request and cancellation request from the E stage 5, and the period of the minimum bus cycle time is At the point in time, the mode switching signal DBGAC is set to H.
“Change the level.

FIG. 2 is a block diagram of a data processing device using the microprocessor according to the present invention shown in FIG. In the figure, 7 is a CPU which is a microprocessor of this invention.
The control signal output from the CPυ7 is given to the first external memory 8 or the second external memory 9 via the selector 10. The first external memory 8 is used for operation in DBG mode, and the second external memory 9 is used for DBGACK mode.
Used for operation in mode. Selector 10 is CPU
When DBGACK is at the "L" level, the first external memory 8 is selected, and when it is at the "H" level, the second external memory 9 is selected.

In the initial state, the CPU 7 outputs the mode switching signal DBGACK at "L" level, and the selector 10 sends the control signal from the CPU 7 to the first external memory 8. This result C
The Pt 17 performs an access operation to the first external memory 8, fetches instructions and data from the first external memory 8, and executes data processing. D on CPU 7 during processing
When a transition to BGACK mode occurs, the mode switching signal DBGACK is set to “H” after waiting for the execution of the currently executing instruction to complete.
Change the level. Due to the change in the mode switching signal DBGACK, the selector 10 switches the control signal from the CPt1 7 from the first external memory 8 to the second external memory 9,
Subsequent access operations from the CPU 7 are performed on the second external memory 9.

During the period when the mode switching signal DBGACK is at the "H" level, data processing is executed not as normal data processing but as exception processing, and after the exception processing is completed, the mode switching signal DB is turned on again.
GACK is returned to the same DBG mode as before the transition to DBG ACK mode, and the process continues.

FIG. 3 is a timing diagram showing the relationship between the change timing of the mode switching signal DBGACM of the microprocessor used in the data processing device shown in FIG. 1 and bus access. The changing point of the mode switching signal DBGACK is at the second cycle of the period assuming the minimum bus cycle. This ensures that the hash I/F unit 6 will not activate the hash cycle and will not access the external bus at the timing when the microprocessor changes the mode switching signal DBGAfJ, regardless of the access time.

By creating a period in which the hash cycle is not executed in this way and switching the mote switching signal DBGACK at the second point in the cycle, the external device can be easily switched using the mode switching signal DBGA (J).

Although this embodiment has been described using switching between the DBG mode and the DBGACK mode as an example, the present invention is not limited to this, and the mode may be any mode. Needless to say, it can be applied in any mode as long as the bus cycle is stopped while outputting.

〔Effect of the invention〕

As explained above, according to the present invention, in a microprocessor used in a data processing device that switches external devices using a mode switching signal, the hash cycle is stopped at the point in time when the mode is switched by the mode switching signal.
It can now be guaranteed that there is no bus access, and even in data processing systems with high-speed buses, external devices can be easily switched using a mode switching signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a pipeline of a microprocessor according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of a data processing device using the microprocessor according to the present invention, and FIG. A timing diagram showing the relationship between the change timing of a mode switching signal and bus access in a data processing device using a microprocessor,
Figure 4 is a system connection diagram of a conventional microprocessor with a mode signal shown in the National Semiconductor manual, and Figure 5 is a timing diagram showing the relationship between the change timing of the mode signal and bus access from the CPU. be. 5... Instruction execution stage 6... Bus I/F section 7.
...cpu s...first external memory 9...second external memory 10...selector In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a microprocessor that has a plurality of operating modes and accesses an external device in a bus cycle based on the operating mode, means for identifying the operating mode; and a mode for switching the operating mode based on the identification result of the means. A microprocessor comprising: means for outputting a switching signal; and bus control means for stopping the bus cycle when the mode switching signal is output.