JPH04162135A - Data processor - Google Patents

Abstract

PURPOSE:To decrease the accesses given to a stack memory in the sub-routine cell and interruption processing operations by storing the return address information in a buffer register provided between a program counter and the stack memory. CONSTITUTION:A buffer register 4 provided between 8 program counter 3 and a stack memory 1 holds the return addresses in the sub-routine cell and interruption processing operations. A control logic circuit 8 controls the transmission of return addresses among the register 4, the counter 5 end the memory 1. Thus the access to the memory 1 can overlap the execution of an instruction having no access to a main memory. Furthermore the access time of the memory 1 can be hidden. As a result, the return address received from the counter 3 is saved and the return address is reset to the counter 3 respectively at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and in particular to a data processing device configured to have a stack memory for storing a return address during subroutine calling or interrupt processing under stored program control. The present invention relates to a data processing device.

BACKGROUND ART Microcomputers are known as stored program controlled data processing devices, and are used in a variety of devices because they can implement various functions using programs stored in memory.

Konomi Computers were first used in devices that performed calculations and data processing, such as calculators and timers, but in recent years, they have been used in applications that operate at high speeds, such as the control of automobile engines and brakes, and even the servo motor control of VTRs. It is also used in devices that detect the state of objects and generate signals to control their operations.

In these real-time processing applications, microcomputers that can perform high-speed processing are desired.
In particular, emphasis is placed on the response speed of interrupt processing, which quickly detects external changes and switches block diagram processing.

An example of a conventional data processing device will be described with reference to the block diagram shown in FIG.

This data processing device outputs the value of the program counter 120 to the address bus 130 as a program address, reads the instruction word from the main memory 10, and reads the instruction word from the data bus 120. The command is fetched into the instruction register 40 via the data bus 30, and the command is interpreted and processed.

For interrupt processing, an interrupt controller 140 is connected to this data processing device (microphone computer), and the interrupt controller 40 detects the occurrence of an interrupt signal and sends it to the interrupt request terminal (INT) of the control unit 10A. This is achieved by inputting a signal. For this control, after executing the interrupt processing program, it is necessary to restart the previous program processing in which the interrupt was accepted, so processing similar to calling a subroutine is performed.

In other words, when accepting an interrupt, the value of program counter 2, which is the address value of the program being executed, is saved in stack memory l, and then the address value of the interrupt processing program is set in program counter 3. Start execution of the interrupt processing program. Further, when the interrupt processing is finished, a return instruction is executed to restore the address value of the saved program from the stack memory 1 to the program counter 3, thereby restarting the interrupted program processing.

Here, the stack memory 1 is a memory with a structure in which the data written last is read out first, and the address of this stack memory 1 is specified by the stack pointer 2,
The stack pointer 2 is incremented or decremented in conjunction with data writing or reading from the stack memory l.

Furthermore, the data width of stack memory 1 is 8 bits (hereinafter referred to as 1
The data width of the program counter 3 is 16 bits (2 bytes).

[Problem to be solved by the invention]

The conventional data processing device described above includes a stack memory 1 with a data width of 1 byte and a program counter 3 with a data width of 2 bytes, and has a structure in which the stack memory 1 is accessed every time a subroutine is called or interrupt processing is performed. Therefore, there is a problem that memory access to the stack memory 1 is slow due to saving and restoring the value of the program counter 3, and processing time increases. In other words, to explain the subroutine as an example, the data width of stack memory 1 is 1
Since the program counter 3 is 2 bytes, in subroutine call comparison, 1 byte is required to determine the calling instruction, and 2 bytes are required to obtain the branch destination address.
There is a Hyde instruction fetch and a 2-high memory write to save the value of program counter 3. When returning from a subroutine, there is a 1-byte instruction fetch to determine the return instruction and a 2-byte memory write to restore the value of program counter 3. There is a 2-byte memory read.

Therefore, the number of accesses to the stack memory 1 is the same as the number of instruction fetches.

It is known that the processing capacity of a data processing device controlled by a store F program is dominated by the speed of memory access, and there is a desire to reduce the aforementioned memory access. Particularly in applications that perform real-time control, interrupts occur frequently, so if access to stack memory can be reduced, total processing capacity can be increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that can reduce access to stack memory during subroutine calls and interrupt processing, and increase processing performance.

5 Means for Solving Problems] The data processing device of the present invention includes a program counter for specifying an address in the main memory, and a program counter that is retained in the program counter when entering branch processing including subroutine calling and interrupt processing. a stack memory that stores a return address of the branch processing that is being executed, and supplies the stored return address to the program counter when returning from the branch processing to processing before the branch; A method for holding a return address from the program counter and transmitting the held return address to the stack memory, and holding a return address from the stack memory and transmitting the held return address to the stack memory. A buffer register is provided for transmitting the program counter data, and a control logic circuit is provided for controlling the transfer of the return address between the buffer register and the program counter and stack memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment includes a stack memory 1 that stores return addresses in subroutine calls and interrupt processing at addresses specified by a stack pointer 2, and a program counter 3 that stores address data for specifying addresses in the main memory. is provided in two stages between the stack memory 1 and the program counter 3, and is used to hold the return address from the program counter 3, transmit the held return address to the stack memory l, and stack memory 1.
a buffer register 4 that holds the return address from and transmits the held return address to the program counter 3;
A+ 4B, indicates whether a valid return address is held in the buffer register 4A, and a buffer status flag register 5, which stores a buffer status flag, and indicates whether a valid return address is held in the buffer register 4B. a buffer status flag register 6 that stores a buffer status flag indicating the buffer status flag; and a stack counter circuit 7 that stores data indicating how many return addresses from the buffer register 4B have been stored in the stack memory 1.
Then, according to the control unit 10, the return address is transmitted between the buffer registers 4A, 411, the program counter 3, and the stack memory l by referring to the data stored in the buffer status flag register 5.6 and the stack counter circuit 7. The configuration includes a control logic circuit 8 for controlling the .

Next, the operation of this embodiment will be explained.

FIG. 2 is a state transition diagram for explaining the operating states of this embodiment, and there are six types of states as shown below.

The first state is immediately after initialization (represented by RESET in Figure 2), and - buffer status flag 5 (represented by BUFA in Figure 2) and buffer status flag 6 (represented by BUFA in Figure 2). The stack counter circuit 7 (indicated by EUFB in Fig. 2) is empty (indicated by Emp in Fig. 2), and the stack counter circuit 7 (indicated by 5TAC in Fig.
) are buffer registers 4a, 4i
This state is indicated as state A in FIG. 2, indicating that no + value is stored in the stack memory 1.

In the 2N state, after the subroutine or interrupt processing is called after initialization (indicated by CALL in Figure 2), the buffer status flag 5 indicates that there is valid data, and the buffer status flag 5 indicates that there is valid data. 6 indicates the sky,
The stack counter circuit 7 is connected to the buffer registers 4A, 4.
In FIG. 2, B is displayed to indicate that the value of is not stored in the stack memory 1 at all.

In the 3151st state, buffer registers 4A and 4B are
/ Since all of them are empty, when the return address is written back from stack memory 1 (indicated by POP in Figure 2), buffer status flag 5 becomes valid data, and the buffer status flag 6 remains empty, and the stack counter circuit 7 fills the buffer registers 4a and 4.
A state indicating that one word of the value of a is stored in the stack memory 1 is indicated as state C in FIG.

In the fourth state, the buffer status flag 5 is set after the subroutine or interrupt processing is called in the second state.
and buffer status flag 6 both indicate valid data, and stack counter circuit 7 registers buffer register 4.
State D in FIG. 2 indicates that the values of A and 4B are not stored in the stack memory 1 at all.

In the fifth state, since the buffer register 4B is empty from the second state, the address to return to is read from the stack memory 1, or the value of the buffer register 4B from the fourth state is stored as the address to return to (the second state). In the diagram, PUSH
) Later, both the buffer status flag 5 and the buffer status flag 6 become valid data, and the stack counter circuit 7 registers the buffer register 4A.
A state indicating that one word of the value +4B has been stored in the stack memory 1 is indicated as state E in FIG.

In the sixth state, since the buffer register 4B is empty, the address to be returned to the stack memory 1 is written back, and both the buffer status flag 5 and the buffer status flag 6 have valid data, and the stack counter circuit 7 is the value 2 of buffer registers 4A and 4m
In FIG. 2, F is displayed to indicate that both words have been stored in the stack memory l.

Here, in this embodiment, buffer registers 4A, 4B
Both have valid data and their values are completely stored in stack memory 1.
If not stored in buffer registers 4A and 4B
from the stack memory l and transfer it to the buffer register 4A.
Alternatively, if the buffer register 43 is empty, a control logic is adopted that transfers the stack memory 1 to the empty buffer register. The state transition shown in FIG. 2 is realized by the control logic described above.

The detailed operation of this embodiment will be explained below with reference to the specific circuit example shown in FIG.

In FIG. 3, numbers l to 7 correspond to stack memory 1 to stack counter circuit 7 shown in FIG. 1, and other parts correspond to control logic circuit 8.

The first buffer status flag register 5, which is composed of a set-reset flip-flop, indicates that valid data is stored as a return address in the buffer register 4A in the set state, and indicates that no valid data is stored in the reset state. , indicating that it is empty. This buffer status flag register 5 is set when it is read from the stack memory 1 when it is in the reset state, when a subroutine is called or when an interrupt process is started, and when the system is initialized (RESET) and the buffer register 4B is set. It is reset when a subroutine in an empty state or a return instruction from an interrupt is executed, and its status signal is output as the buffer status flag A.

The second buffer status flag register 6, which is composed of a set-reset flip-flop, indicates that valid data is stored in the buffer register 4B as a return address in the set state, and indicates that it is empty in the reset-set state. . This buffer status flag register 6 is used for reading from the stack memory l when there is valid data in the buffer register 4A, and for reading from the stack memory l when there is valid data in the buffer register 4A.
It is set when a subroutine is called or interrupt processing is started when there is valid data in A, and the system is initialized.
It is reset when a sub-latin or interrupt return instruction is executed.

Stack counter 71 includes buffer registers 4A, 4.
Indicates how many words have been stored in the stack memory 1, and is cleared to 0 when the system is initialized, and is incremented when writing or reading stack memory 1, and both buffer registers 4A and 4B have valid data. Command to call the subroutine or start interrupt processing at the time, and return from the subroutine and interrupt when its own count value is "2" or when the count value is "1" and the buffer register 4B is empty. is decremented by the execution of .

The decoder 72 decodes the value of the stack counter 71 and supplies each part of the control logic circuit 8 with a signal indicating how many words of data are stored in the stack memory l.

Logic gate G8 receives a return instruction (from a subroutine or interrupt) when both buffer registers 4A and 4B are empty.
This circuit detects an attempt to execute a command (represented by RET in the figure), and transmits this output to the microcomputer control unit 10 to suspend execution of the return command.

Logic gate G9 detects an attempt to call a subroutine or start interrupt processing when both buffer registers 4A+4a are valid data and these values are not stored in stack memory 1 at all. The circuit also transmits this output to the control unit 10 of the microcomputer to suspend the above-mentioned operation.6 Logic Game) Gl 8. The GIO determines the conditions for reading the data at the return address from the stack memory l to the buffer registers 4A and 4□, and obtains from the inversion circuit IVI that the main memory 110 is not being accessed for microcomputer instruction processing. If either the buffer register 4A or the buffer register 4B is empty, a read operation from the stack memory 1 (indicated by POP in the figure) is activated.

Logic game) GII is the noguffa register 4A.

The condition for storing the data at the return address from 4B to stack memory 1 is determined, and when buffer registers 4A and 4B both have valid data and the microcomputer is not accessing main memory 110 for instruction processing, Start the write operation (displayed as F'USH in the figure).

The buffer registers 4A and 4B have five types of operations as shown below.

(1) Calling a subroutine and starting interrupt processing (C in the diagram)
(indicated by AL, L), if logic gate G9 does not determine that the CALL should be suspended, the value of buffer register 4A is transferred to buffer register 4B, and the value of program counter 3 is transferred to buffer register 4A. Transfer to.

(2) Returning from a subroutine or interrupt processing (RET in the figure)
If it is not determined in logic game G8 that RET should be suspended, the value of buffer register 4A is transferred to program counter 3, and the value of buffer register 4A is transferred to program counter 3. The value of l is transferred to the buffer register 4A.゛(3)! buffer register 4A at control gate G11.

When it is determined that the value of buffer register 4B should be stored in stack memory 1 (indicated by PUSH in the figure), the value of buffer register 4B is transferred to stack memory 1, and the value of stack pointer 2 is modified.

(4) Logic game) From stack memory 1 with Gl O...
Return address to Tufa registers 4A and 411 (P in the figure)
If it is determined that the buffer status flag A output from the buffer status flag register 5 indicates an empty state, the data is read from the stack memory 1 and transferred to the buffer register 4A, and the stack is Modify the value of pointer 2.

(5) If it is determined that the return address should be restored from the stack memory 1 of the logic gate G10 to the buffer registers 4A and 4B, and the output buffer status flag A of the buffer status flag register 5 indicates that there is valid data, the stack memory The data is read from 1 and transferred to buffer register 4B, and the value of stack pointer 2 is modified.

In (3) to (5) above, stack pointer 2 is modified by accessing stack memory l, and normally stack pointer 2 is decremented before writing to stack memory 1, and reading from stack memory 1 is After that, an operation is performed to increment stack pointer 2.

However, among the state transitions in FIG. 2, in the transition from state F to state E and from state E to state D, the buffer register 4A is
, 4B, the stack pointer 2 is decremented so that the valid data can be read out from the stack memory 1 again.

Next, as an example of overall operation, a case where subroutines with double nesting levels are called will be described with reference to the state transitions in FIG. 2.

Normally, after system initialization, it will be in state A.
Since the buffer register 4A or the buffer register 4B is in an empty state, reading from the stack memory I is performed twice, and a transition is made to state F via state C.

Here, when the subroutine is called, the value of the program counter 3 is stored in the buffer register 4A while the value of the buffer register 4A is transferred to the buffer register 4B, and a transition is made to state E. At this time, buffer registers 4A, 4. The transfer is only within ll, and no access to stack memory 1 occurs.

Furthermore, when the subroutine is called, the value of the program counter 3 is transferred to the buffer register 4A again while the value of the buffer register 4A is transferred to the buffer register 4°.
, and transitions to state D. In this state, the values of the buffer registers 4A and 4T3 are not stored in the stack memory 1 at all, so writing to the stack memory 1 is started, and when the writing is completed, a transition is made to state E.

Next, when a return instruction from the subroutine is executed, the value of the buffer register 4B is returned to the program counter 3 while the value of the buffer register 4A is returned to the program counter 3.
Transfer to A and transition to STATE)C.

In state C, since the buffer register 4B is empty, reading of data at the return address from the stack memory 1 is started, and a transition is made to state F when the reading is completed.

Furthermore, when a return instruction from a subroutine is executed,
While returning the value of the buffer register 4A to the program counter 3, the value of the buffer register 43 is transferred to the buffer register 4A, and a transition is made to state C. Thereafter, reading from the stack memory 1 is performed again, and the process settles on stage (F).

Therefore, whereas in the conventional data processing apparatus, the stack memory 1 is accessed four times, in this embodiment, the access can be accessed only three times. Furthermore, if the nesting level of the subroutine is one, the stack memory 1 is accessed once because the call □ transitions from state F to state E, and then returns to state F via state C. only occurs.

As explained above, in the embodiment of the present invention, two words of return address information are stored in two buffer registers, so if the nesting level is two or less, the number of accesses to the stack memory can be reduced. can. Furthermore, access to the stack memory 1 is executed by detecting that there is no access to the main memory 110 while the microcomputer is enabling or disabling interrupts or operating internal registers. Even if accesses occur, the stack memory 1 prevents the processing speed from decreasing, allowing high-speed processing to be performed.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

In the first embodiment, there are two buffer registers 4A.

Although 2 words of the return address are stored using 4-Yo, it is expected that the processing speed will be improved without reducing the number of accesses to the stack memory 1, so in this second embodiment, the number of buffer registers 4 is reduced to one. This reduces the amount of hardware.

Next, the operation of this embodiment will be explained.

FIG. 5 is a state transition diagram for explaining the operation of this embodiment, and there are three types of states as shown below.

In the first state, immediately after initialization, the buffer status flag register 5 (indicated by state in Figure 5) is empty, and the stack status flag register 9 (indicated by 5TACK in Figure 5) is empty. State J in FIG. 5 indicates that the value of the buffer register 4 is not stored in the stack memory 1.

In the second state, after the subroutine or interrupt processing is called after initialization, the buffer status flag register 5 indicates that there is valid data, and the stack status flag register 9 transfers the value of the buffer register 4 to the stack memory 1.
The state shown in FIG. 5 indicates that the state is not stored in the state.

The status of the third bacterium is determined by the buffer status flag register 5 because valid data is held in the buffer register 4.
is set, and the value is stored in the stack memory 1 (*). This state is indicated by the stack state flag register 9 as state L in FIG.

This embodiment employs a control logic that stores valid data in the stack memory 1 if the buffer register 4 has valid data, and transfers the value from the stack memory 1 to the buffer register 4 if the buffer register 4 is empty. This control logic realizes the state transition shown in FIG.

Next, the detailed operation of this embodiment will be explained in FIGS. 4 and 5.
This will be explained with reference to the figures.

The buffer status flag register 5 indicates that valid data is stored as a return address in the buffer register 4 in a set state, and indicates that no valid data is stored in the buffer register 4 as a return address, that is, it is empty. This buffer status flag register 5 is set when a subroutine is called or interrupt processing is activated, and is reset when the system is initialized (RESET) and a return instruction from the subroutine or interrupt is executed.

The stack state flag register 9 indicates that the value of the buffer register 4 is stored in the stack memory 1 in the cellar state, and indicates that it is not stored in the reset state. This stack state flag register 9 is the buffer register 4.
It is set by storing or reading the value in stack memory 1, and is reset when the system is initialized, a subroutine is called or interrupt processing is started, and a return instruction from a subroutine or interrupt is executed.

Logic gate G8 is a circuit that detects an attempt to execute a return instruction from a subroutine or interrupt (indicated by RET in the figure) when the buffer register 4 is empty, and its output is controlled by the microcomputer. The department will also be notified and the execution of the return order will be put on hold.

Logic gate G9A is a circuit that detects an attempt to call a subroutine or start interrupt processing when there is valid data in buffer register 4 and the value is not yet stored in stack memory 1. The output is also transmitted to the control section of the microcomputer to suspend the aforementioned operations.

The logic gate G10A determines the conditions for reading the data at the return address from the stack memory 1 to the buffer register 4, and obtains from the inversion circuit IVI that the microcomputer is not accessing the main memory for instruction processing.
If the buffer register 4 is empty and the stack status flag register 9 is reset), a read operation from the stack memory 1 (indicated by POP in the figure) is activated.

Logic gate GlIA determines the conditions for storing data at the return address from buffer register 4 to stack memory 1, and if there is a valid take in buffer register 4 and stack state flag register 9 is in a reset state, the microcomputer starts processing instructions. Write operation to stack memory 1 (when main memory is not accessed for
(indicated as PUSH in the figure).

In this embodiment, as shown in the state transition diagram of FIG.
When a subroutine is called or an interrupt process is activated, a transition is made to state K, a transfer from buffer register 4 to stack memory l is performed, and state is changed to state (L). Further, by executing a return instruction from the subroutine and interrupt processing, the state is transited to state J, where the transfer from the stack memory 1 to the buffer register 4 is performed, and the state becomes state (L).

Therefore, when calling or returning, the buffer register 4 is always
Transfer is performed between the stack memory 1 and the stack memory 1, but since access to the stack memory 1 is performed when the main memory is not accessed during instruction processing, the access to the stack memory 1 does not reduce the processing speed and can be performed at high speed. can be processed.

In both embodiments, the circuit detects that buffer registers 4.4A and 4B are empty immediately after system initialization, and transfers data from stack memory 1 to buffer registers 4.4 and 4.4B. However, by determining the upper limit of stack pointer 2 using a comparator, etc., or by counting the number of words stored in stack memory 1,
Reading from the stack memory 1 based on determination of whether the buffer registers 4.4A, 41] are free may be prohibited.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which a control logic circuit is provided between the program counter and the stack memory to control the transmission of a discrete return address that holds a return address in subroutine calls and interrupt processing. This allows stack memory access to be interrupted by the execution of instructions that do not access main memory, and the stack memory access time can be hidden, so the return address from the program counter can be saved and the return address to the program counter can be saved. This has the effect of allowing high-speed recovery processing.

[Brief explanation of drawings]

1 and 2 are a block diagram showing a first embodiment of the present invention and a state transition diagram for explaining the operation of this embodiment, respectively, and FIG. 3 is a block diagram of the embodiment shown in FIG. 1. FIGS. 4 and 5 are circuit diagrams showing specific circuit examples, and FIGS. 4 and 5 are respectively circuit diagrams showing a second embodiment of the present invention and state transition diagrams for explaining the operation of the embodiment. FIG. 6 is a conventional circuit diagram. 1 is a block diagram showing an example of a data processing device of FIG. 1...Stack memory, 2...Stack pointer, 3...Program counter, 4.4
A, 4B...Buffer 7 register, 5, 6...
...Buffer status flag register, 7...
...stack counter circuit, 8.8A ...control logic circuit, 9 ...stack state flag register,
10.10A...Control! , 20... Take buffer circuit, 30... Internal data bus, 40...
...Instruction register, 50...Tefuda, 60.
... Address latch circuit, 70 ... Address buffer circuit, 71 ... Stack counter, 72 ... Tekoter, 110 ... Main memory, 120 ... ...Take bus, 130...
・Address bus, 140... Interrupt controller, 01 to G22. G9A~Gl IA, Gl 5A・
...Logic gate, INI~IN4...Inverter. Agent Patent Attorney Susumu Uchihara ＼1 RESET Figure 2 RESE No. 5

Claims (1)

[Claims] 1. A program counter for specifying an address in main memory, and a return address of the branch process held in the program counter when entering a branch process including calling a subroutine and interrupt process. and a stack memory for supplying the stored return address to the program counter when returning from the branch processing to the processing before the branch, wherein the A buffer that holds a return address from the program counter and transmits the retained return address to the stack memory, and holds a return address from the stack memory and transmits the retained return address to the program counter. A data processing device comprising a register and a control logic circuit for controlling transmission of the return address between the buffer register and the program counter and stack memory. 2. The data processing device according to claim 1, wherein the buffer register is configured in multiple stages. 3. A first flag register that stores a buffer status flag indicating whether or not a valid return address is held in the buffer register, and a stack that indicates that the return address held in the buffer register is stored in the stack memory. a second flag register for storing status flags, and a control logic circuit is provided between the buffer register and the program counter and stack memory according to the values of the flags stored in the first and second flag registers. 2. The data processing apparatus according to claim 1, wherein said data processing apparatus is configured to control transmission of said return address.