JP2591211B2 - High-speed interrupt processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed interrupt that can improve interrupt responsiveness by interrupting a currently executing instruction when an interrupt occurs and immediately executing an interrupt process. The present invention relates to a processing device.

2. Description of the Related Art Conventionally, if there is an instruction being executed when an interrupt occurs, it has been general to execute an interrupt processing program after executing the instruction to the end.

According to this, according to this method, even if the instruction being executed at the time of the occurrence of the interrupt is in a data reading state or a writing state, the instruction is executed to the end uniformly.
In the case of a multiplication / division instruction requiring a long time for the sequence of the operation unit, even if an interrupt occurs, the instruction is executed to the end, so that it takes time to activate the interrupt processing program. Furthermore, when designing a system, interrupt responsiveness is a factor that affects the throughput of the system, and the response time when an interrupt occurs during execution of an instruction such as a multiplication / division instruction that takes a long time to perform an arithmetic operation is the worst case. Therefore, the system was designed based on the response time, and it was important to shorten the interrupt response time.

The present invention solves the above-mentioned conventional problems, and by immediately stopping an instruction being executed at the time of receiving an interrupt,
It is an object of the present invention to provide a high-speed interrupt processing device that realizes a high-speed interrupt response.

Means for Solving the Problems In order to solve the problems, the high-speed interrupt processing apparatus of the present invention: (a) If an instruction being executed when an interrupt occurs is not a write cycle, the instruction is immediately stopped.

(B) Always keep a backup of the contents of the register file, immediately stop the instruction and accept the interrupt.

(C) When an interrupt occurs, if the instruction being executed is a register access, the instruction is immediately stopped. If the data area such as the RAM is being accessed, the instruction is executed to the end.

It is configured as follows.

Operation With this configuration, the instruction being executed can be stopped when an interrupt occurs while minimizing the load on the hardware, and high-speed interrupt responsiveness can be realized.

Examples Hereinafter, examples of the present invention will be described.

FIG. 1 is a block diagram showing a configuration of a high-speed interrupt processing apparatus according to an embodiment of the present invention, in which, when an interrupt occurs, if the currently executed instruction is not in a write cycle, the currently executing instruction is immediately interrupted and interrupt processing is performed. FIG. The interrupt acceptance permission determining unit 1 is a write cycle latch 2 (hereinafter, write cycle latch) indicating whether or not a write cycle is present.
And a gate circuit 4 to which an instruction end signal latch 3 indicating the end of the instruction is input.
Is output. Whether each instruction is a write cycle or the last cycle of an instruction is determined by outputting information from the micro ROM 7, updating the information for each instruction, and transmitting the updated information to the interrupt acceptance permission determining unit 1. You. The interrupt unit 6 receives the interrupt acceptance permission signal 5 and determines whether or not interrupt processing can be started. In a microprocessor or microcomputer, if the instruction set does not include instructions that repeat read and write operations, and if such instructions are not used in software, a simple gate configuration can be used, such as multiplication and division. The instruction can be immediately stopped while executing the instruction whose operation cycle is very long like the instruction, and the interrupt responsiveness is improved.

FIG. 2 is a sequence diagram showing an operation of stopping the instruction currently being executed. If an interrupt occurs during the execution of an instruction and the instruction is an execution cycle (including a read cycle) other than a write cycle, execution of the instruction is interrupted and interrupt processing is performed. Therefore, in the instruction execution cycle, the interrupt process is executed earlier by the write cycle and the interrupted cycle, and the interrupt responsiveness is improved.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention in which a register file is backed up every time one instruction is executed, an instruction being executed is immediately interrupted when an interrupt occurs, and interrupt processing is performed. It is. The data of the register file 8 is transferred to the backup file 11 by the backup control unit 10 every time the last cycle signal 9 of each instruction is generated, that is, for each final state of each instruction. The register file is backed up for each instruction. Therefore, if the instruction being executed at the time of the interrupt is not a write cycle, the currently executing instruction can be interrupted and the interrupt processing can be executed immediately. Since the same data as described above can be used, the operation data is guaranteed, and the register save processing required at the time of accepting the interrupt is not required, so that the interrupt responsiveness is improved and the load on the software is reduced.

FIG. 4 shows still another embodiment, in which, when only a register file access is performed, an instruction being executed is interrupted when an interrupt occurs and the interrupt is accepted. FIG. 4 is a block diagram showing a configuration of a device that executes an instruction to the end and receives an interrupt. The interrupt acceptance permission judging section 12 receives the write cycle signal latter 2, the instruction end signal latch 3, and the RAM access signal latch 14, and generates an interrupt acceptance permission signal 5 by a gate circuit. The write cycle signal latch 2 is a signal latch indicating whether or not there is a write cycle in the instruction execution. The instruction end signal latch 3 is a signal latch indicating whether or not the last cycle of the instruction. The RAM access signal latch 14 is This is a signal latch indicating whether or not a RAM access other than the register has been made during the instruction. When there is no RAM access other than the register and there is no write access, the interrupt acceptance permission signal 5 becomes active. When there is RAM access or write access, the interrupt acceptance permission signal 5 becomes active when the instruction reaches the last cycle. Becomes active.
The interrupt acceptance permission signal 5 is input to the interrupt unit 6, and it is determined whether or not interrupt processing is possible. Write cycle signal latch 2, instruction end signal latch 3, RAM access signal latch 14
Is determined by the micro ROM unit 7 in what cycle the instruction is in, and each is input. In microprocessors and microcomputers in which basic operations are performed by register operations, when an interrupt occurs, the instruction being executed can be interrupted to receive the interrupt, and the data management can be limited to the data in the register. It is reduced. In addition, RAM data is often used for data communication between tasks, and even if it is read data, the data may be changed.If there is RAM data access, execute until the end of the instruction. ,
By accepting the interrupt, the load on the software is reduced, and the software can be easily assembled mainly on the register operation. Therefore, the interrupt response can be performed at substantially high speed.

Effects of the Invention As described above, according to the present invention, interrupt processing can be performed at high speed, high-speed response can be realized, and it is difficult to execute again.
By interrupting the instruction after accessing the data after executing the instruction, the load on hardware and software can be minimized, and the speed of interrupt reception can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a high-speed interrupt processing apparatus according to one embodiment of the present invention, FIG. 2 is a sequence diagram for stopping a currently executing instruction, and FIG. 3 is a configuration of another embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of still another embodiment. 1, 12 ... interrupt acceptance permission judgment section, 2 ... write cycle signal latch, 3 ... instruction end signal latch, 4, 13 ... gate circuit, 5 ... interrupt acceptance permission signal, 6 ... interrupt section,
7: Micro ROM, 8: Register file, 9:
Each instruction write cycle signal, 10 ... backup controller, 11 ... backup file, 14 ... RAM access signal latch.

Claims (2)

(57) [Claims] 1. A microcomputer or a microprocessor having an instruction set that does not include an instruction for repeating a series of read / write operations twice or more in a data space or a continuous transfer instruction for a register group with one instruction. A ROM, an interrupt acceptance permission determination unit, and an interrupt unit,
The interrupt acceptance permission determination unit receives, as input information from the micro ROM, information as to whether or not the instruction being executed is a write cycle and information as to whether or not the instruction is in an instruction end cycle. Sometimes, when the instruction being executed is not in a write cycle and when the instruction is completed, an interrupt acceptance permission signal is output to the interrupt unit to immediately suspend the instruction.
A high-speed interrupt processing device which stops and accepts the interrupt processing. 2. A microcomputer or microprocessor constructed by a register operation method, comprising: a micro ROM, an interrupt acceptance permission judging section, and an interrupt section, wherein the interrupt acceptance permission judging section receives input information from the micro ROM. As an input, information as to whether or not the instruction being executed has a write cycle, information as to whether or not it is the last cycle of the instruction, and information as to whether or not there is a RAM access are input. If there is no RAM access other than the register during execution and there is no write cycle, an interrupt acceptance permission signal is output to the interrupt unit to immediately suspend and stop the instruction to accept the interrupt processing;
If there is a RAM access or write cycle during execution of one instruction, an interrupt acceptance permission signal is output to the interrupt section at the end of the instruction to accept the interrupt processing.