JP3328867B2 - Multiprocessor arithmetic device and programmable controller having the device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor arithmetic unit in which each instruction is executed by a master processor or a slave processor, and a programmable controller having such a unit.

[0002]

2. Description of the Related Art In a multiprocessor arithmetic device such as a programmable controller, a master processor such as an ASIC for executing basic instructions at high speed and a slave processor for executing other applied instructions by a general-purpose MPU (one unit) are usually used. However, a plurality of units may be used.)

A master processor decodes an instruction from an instruction memory, determines whether the instruction is to be executed by the master processor or a slave processor, and allows the own processor to execute the instruction. These instructions are executed by the master processor, and those executed by the slave processor are sent as data to the slave processor.

[0004] On the other hand, the slave processor is normally inactive or the like, and when receiving an instruction to be executed on the slave processor side from the master processor, the slave processor analyzes and executes the instruction.

That is, for example, when there are three operands of an instruction to be executed, when the slave processor receives an instruction from the master processor, it interprets the instruction (step 100) and calculates the address of operand 1 (step 100) as shown in FIG. 110), data fetch of operand 1 (step 120), address calculation of operand 2 (step 130), data fetch of operand 2 (step 1)
40) Processing in the order of operation of data by operand 1 and data by operand 2 (step 150), calculation of destination (transfer destination) address by operand 3 (step 160), and writing to destination (step 170) It is carried out.

[0006]

However, in such a conventional multiprocessor arithmetic unit, the slave processor also interprets the instruction as shown in FIG. 7, and then addresses according to each operand. The calculation was performed to obtain the source data used for the operation of the instruction, the destination address was calculated, and then the actual operation was started, so the actual operation was performed after the operation request was delivered to the slave processor. It takes time to start the process, and the overhead in the slave processor increases.

Accordingly, the present invention has been made in view of such a problem, and provides a multiprocessor arithmetic device capable of reducing the overhead of arithmetic processing on the slave processor side, and a programmable controller having the multiprocessor arithmetic device. The purpose is to:

[0008]

To achieve the above object, according to an aspect of, in the first aspect of the present invention, Masutapuro set each instruction
A multiprocessor arithmetic unit configured to be executed by a slave processor or a slave processor, wherein the master processor analyzes an instruction and executes the instruction on the master processor side or is executed on the slave processor side And outputs a calculation instruction to the master processor or the slave processor based on the result of the determination, and decode means for outputting an operand of the instruction, and calculates an address based on the operand from the decode means. Address calculating means for storing the address calculated by the address calculating means .
Address storage means, data to slave processor side
Port and increment data port, the above address
Access to slave data by slave computing means
While comprising interfacing means for chromatic access control means, and the slave processor accesses to the interface means receives an operation instruction from the decode unit, reads out the data of the address which is stored in the interface means Equipped with slave operation means to execute
And the slave operation means accesses the data port.
If the address is indicated in the slave operation means,
Direct access to the data and increment data port
Access to the slave operation means,
Direct access to the data indicated by the address
Increments the address stored in the address storage means.
Characterized in that so as to cement.

Further, according to the invention described in claim 2, according to claim 1,
User program by the described multiprocessor arithmetic unit
Running the ram .

[0010]

[0011]

[0012]

According to the present invention, on the master processor side, the decoding means analyzes the instruction and determines whether the instruction is executed on the master processor side or on the slave processor side. An operation instruction is output to the master processor or the slave processor based on the result, an operand of the instruction is output, an address calculation unit calculates an address based on the operand, and the interface unit stores the address.

When the slave operation means on the slave processor side accesses the interface means in response to the operation command from the decoding section, the data of the address stored in the interface means is read out under the control of the interface means, and the data is read out. Execute.

The interface means stores the address calculated by the address calculation means, and when the slave calculation means accesses the data port, causes the slave calculation means to directly access the data indicated by the address ;
If you access the increment data port,
The slave operation means directly sends the data indicated by the address.
Access, and increment the address.
To Tosuru control.

[0015]

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multiprocessor arithmetic unit according to the present invention and a programmable controller having the same will be described below with reference to the drawings.

FIG. 1 shows the configuration of a multiprocessor arithmetic unit according to the present invention.

This multiprocessor arithmetic unit is provided in a programmable controller, and has a plurality of (two in this embodiment, for convenience) processors, namely a master processor 1 and a slave processor 2.
And a user program memory 3 storing a user program, and a data memory 4 as basic components.

The master processor 1 includes a decoding unit 11
, An operand analysis unit 12, a master operation unit 13, and an interface unit 14.

Here, the decoding unit 11 reads and analyzes the instruction from the user program memory 3 and determines whether the instruction is executed on the master processor 1 side or on the slave processor 2 side. Then, based on the result of the determination, an operation instruction is output to the master processor 1 or the slave processor 2 and the operand of the instruction is output. Note that the decoding unit 11 causes the master processor 1 to execute an instruction requiring a high-speed operation such as a basic instruction in principle, and causes the slave processor 2 to execute an applied instruction or an instruction created by a user later. Judge.

The operand analyzing unit 12 includes a decoding unit 11
Address calculating unit 1 which calculates an address based on an operand from and outputs it to a data fetch unit 12b and an address register 14a of the interface unit 14 which will be described later.
And 2a, the when the instruction is executed by the master processor 1 side based on the determination result of the decoding unit 11 accesses the data memory 4 based on the address of the address <br/> calculator 12a has calculated data And a data fetch unit 12b for reading and sending the data to the master operation unit 13. The data fetch unit 12b sends an instruction to the master processor 1 based on the result of the determination by the decode unit 11.
Even when the data is read out from the data memory 4 and sent to the master operation unit 13 only when the instruction is executed on the side, the instruction always reads out the data and sends it to the master operation unit 13 based on the judgment result of the decoding unit 11. You may do it.

In the present embodiment, the master calculation unit 13
A high-speed operation of a specific instruction such as an IC is performed. Upon receiving an operation instruction from the decoding unit 11 to the master processor 1 side,
The data fetch unit 12b of the operand analysis unit 12 is configured to input the data read from the data memory 4 and execute a calculation based on the calculation command.

The interface unit 14 comprises an address register 14a for storing the address of the instruction calculated by the address calculation unit 12a as an address of an instruction executed on the slave processor 2 side by side for each instruction, and an interface controller 14b. Have been.

The interface controller 14b has a data port 14b1 and an increment data port 14b2 accessible from the slave processor 2 side.
When the access to b1 is made, the address stored in the register 14a is output to an address bus to control the memory access so that the slave processor 2 can directly access the data memory 4.
When the slave processor 2 accesses the increment data port 14b2, the slave processor 2 sets the data memory 4 based on the address stored in the access register 14a.
It is configured to control the memory access so as to allow direct access to, and then increment the address stored in the access register 14a by one.

On the other hand, the slave processor 2 does not include an instruction decoding unit, but receives an instruction operation instruction from the decoding unit 11 of the master processor 1 and follows the processing procedure shown in FIG. A slave operation unit 21 for accessing the data port 14b1 or the increment data port 14b2 of the interface controller 14b and executing the operation.

FIG. 2 shows an instruction operation procedure in the slave operation unit 21 of this embodiment.

When the slave operation unit 21 of this embodiment receives an operation command from the decoding unit 11 of the master processor 1, it starts a slave operation process, and first interprets the operation instruction (step 200). For example, it interprets whether the operation instruction instructs access to the data port 14b1 or access to the increment data port 14b2, and interprets the number of operands of the instruction. Here, it is assumed that there are three operands, that is, two source operands indicating the address of the source data of the instruction to be operated and one destination operand indicating the destination of the operation result. I do.

Based on the interpretation, the slave operation unit 21 accesses one of the data port 14b1 and the increment data port 14b2 and accesses the data memory indicated by the address of the operand 1 stored in the address register 14a. 4 and directly fetches the data at the address of operand 1 (step 210).

Next, the port access is similarly performed to fetch the data at the address of operand 2 (step 2).
20) Then, the both fetched data are operated according to the operation instruction (step 230), and the operation result is transferred to the destination indicated by the address of the operand 3 stored in the address register 14a by the third port access. (Step 240), the arithmetic processing of this instruction ends.

Therefore, according to the present embodiment in which the processing shown in FIG. 2 is executed on the slave processor 2 side, steps 110 and 130 are compared with the prior art in which the processing shown in FIG. The calculation of the source data address, which is the calculation of operands 1 and 2, and the calculation of the destination address, which is the calculation of operand 3 in step 160, become unnecessary, and the overhead on the slave processor 2 side is reduced. Is reduced, and a high-speed operation on the slave processor 2 side becomes possible.

Next, the operation of the thus-configured master processor arithmetic unit will be described using specific instructions as an example.

FIG. 3 shows an example of a specific instruction.

This instruction indicates an ADD (addition) instruction 31 which is executed on the slave processor 2 side, and includes an instruction code "ADD" indicating the content of the operation, and first to third three.
And one operand.

The contents of the operation of the ADD instruction 31 are as follows. "The data at address 12 (of the first operand) and the data at address IR0 + 4 (of the second operand) are added, and the addition result is expressed as ) Write to the data at the address indicated by the data at the address 18. "

It is assumed that IR0, that is, address 0 of the user program memory 3 contains data of a constant "10".

FIG. 4 shows an example of the data storage state of the data memory 4 before the execution of the ADD instruction 31.

In this data memory 4, for example, an address of "address 8" contains data of a constant "8" and an address of "address 11".
Data is stored in the address in the order of addresses, such as data of a constant "1".

On the premise of the above memory state, when the ADD instruction 31 shown in FIG. 2 is read from the user program memory 3 by the decoding unit 11 of the master processor 1 and analyzed, the decoding unit 11 An operation command indicating the operation content of the ADD instruction 31 is sent to the processor 2 and the first instruction of the ADD instruction 31
To the third operand (see FIG. 2) are the operand analyzer 1
2 is sent.

In the operand analyzer 12, the first to third operands are received by the address calculator 12a, and the address is calculated as follows.

That is, in the case of the first operand, "オ ペ ラ ン ド
Since the address is directly specified as "12", the address calculation result is the constant "12" as it is, and this is written to the address register 14a.

In the case of the second operand, "# 4 (I
R0) ", the content" 10 "of IR0 is read, the operation" IR0 + 4 "is executed to obtain" 14 ", and the calculation result" 14 "is written to the address register 14a.

In the case of the third operand, "$ 18"
The address calculation result is a constant "18" as it is, and this is written to the address register 14a.

Therefore, three addresses respectively corresponding to the first to third operands of the ADD instruction 31 are stored in the address register 14a.

In the slave processor 2, the slave processor 21 receives an operation instruction of the ADD instruction 31 from the decoder 11 on the master processor 1 side, and the slave processor 21 interfaces with the slave in accordance with the operation instruction of the ADD instruction 31. Data port 14b1 of controller 14b or increment data port 14b
2 is accessed to perform read and write operations.

First, when the slave operation unit 21 accesses the data port 14b1 and performs a read operation, the interface controller 14b outputs each address stored in the address register 14a to the address bus, thereby outputting the address. , The address of the first operand stored in the address register 14a, "12", is read from the address register 14a and sent to the address bus.

Then, as shown in FIG.
Constant "2" which is the data content of the address "address 12"
Is read from the data memory 4 into the slave processor 2 via the data port 14b1 as read data.

Similarly, the slave operation unit 21
The second data calculated on the master processor 1 side can be obtained simply by accessing the increment data port 14b2 again.
The constant “4”, which is the data at the address “14” of the operand, can be read from the data memory 4 .

Then, the slave operation unit 21 decodes the constant “2” based on the address of the first operand and the constant “4” based on the address of the second operand on the decoding unit 11.
A constant "6" is obtained by addition in accordance with the ADD operation command from the CPU, and the data port 14b1 is accessed in accordance with the operation command to write the operation result "6".

Then, only by making a write access to the data port 14b1, the interface controller 14b
By the memory access control of the third operand, the address "8" of the third operand stored in the address register 14a
The address is output to the address bus, and the constant "6" of the operation result is written to the address "8" of the data memory 4.

FIG. 5 shows the contents of the data memory 4 after the execution of the ADD instruction 31. As shown in FIG. 5, the contents of the address "8" of the data memory 4 are changed to a constant "6". You can see that.

Therefore, according to the present embodiment, as shown in FIG. 2, the slave processor 2 does not calculate the address based on the operand of the instruction, and the data port of the interface controller 14b on the master processor 1 side. By simply accessing 14b1, data can be read from the data memory 4 by the memory address control of the interface controller 14b to execute the operation, and the operation result can be written to the destination.

Therefore, as shown in FIG. 6, the source data address which is the calculation of operands 1 and 2 in steps 110 and 130 is compared with the prior art in which access calculation is also performed on the slave processor 2 side based on each operand. And the calculation of the destination address, which is the calculation of operand 3 in step 160, is not required, the overhead on the slave processor 2 side is reduced, the burden on the slave processor 2 side is reduced, and the slave processor 2 side is reduced. High-speed operation becomes possible.

Next, in this embodiment, the decoding unit 11
The case where the slave operation unit 21 accesses the increment data port 14b2 of the interface controller 14b based on the operation command from the CPU will be described.

This increment data port 14b2
Is accessed by the instruction decoded by the decoding unit 11,
For example, in the case of a block copy instruction for data in which data in a certain area from a certain address to a certain address in the data memory 4 is copied to another area in block units, each data in the certain area is calculated and stored in another area. This is performed in the case of a batch processing instruction or the like in block units such as a writing instruction.

That is, assuming that the slave operation unit 21 receives an operation instruction such as a batch processing instruction for processing data in such a block unit from the decoding unit 11, the slave operation unit 21 transmits the data port 14b1 of the interface controller 14b. Instead, access the increment data port 14b2.

In the case of such a block transfer instruction, since the head address of the data block is stored in the address register 14a (for example, the address "9" is stored), the slave operation is performed. When the section 21 accesses the increment data port 14b2, the interface controller 14b outputs the address of the head address "9" to the address bus, and sends the increment data port 14b2 to the slave operation section 21.
Directly access the data memory 4 via the “9”
The constant "9" which is the data of the "address" is read, and arithmetic processing such as copying in block units can be executed.

At that time, when the arithmetic processing is completed, the interface controller 14b sets the address of each operand stored in the address register 14a to 1 because the access is to the increment data port 14b2.
Increment.

Then, when the slave operation unit 21 accesses the increment data port 14b2 again, the slave operation unit 21 controls the data of the address "10" which is stored in the address register 14a and is incremented by one under the control of the interface controller 14b. Can be accessed, and the address register 14a can be accessed by accessing the increment data port 14b2 again.
Is incremented by one again, and at the time of the next access, the data at the next address “11” can be accessed.

Therefore, according to the present embodiment, the slave arithmetic unit 21 reads out and executes data in a certain area only by repeating access to the increment data port 14b2 by the required number of data without performing address calculation. Therefore, even in the case of batch processing of data in a certain area, high-speed operation can be performed without performing address calculation.

[0060]

As described above, according to the present invention, the address calculated by the address calculation means based on the operand of the instruction is stored in the interface means, and the slave calculation means on the slave processor side accesses the interface means. Since the interface means performs access control so that the slave operation means can access the data of the stored access, the slave processor does not calculate the address based on the operand of the instruction. Data can be read and executed.

Therefore, compared with the prior art in which the access calculation is also performed on the slave processor side based on each operand, the calculation processing of the source data address and the destination address becomes unnecessary, and the overhead on the slave processor side is reduced. Thus, the load on the slave processor is reduced, and high-speed operation on the slave processor is enabled.

According to the present invention, when the slave operation means accesses the increment data port, the slave operation means is directly accessed to the data indicated by the address and the address is incremented. By simply repeating the access to the increment data port by the required number of data, it is possible to read and execute data in a certain area without performing address calculation. High-speed operation is possible.

[Brief description of the drawings]

FIG. 1 shows a first example of a multiprocessor operation device according to the present invention.
FIG. 2 is a block diagram showing an embodiment.

FIG. 2 is a flowchart illustrating a procedure of an instruction operation process in a slave operation unit according to the first embodiment.

FIG. 3 is an explanatory diagram showing specific instructions.

FIG. 4 is an explanatory diagram showing an example of a data storage state of a data memory before execution of an instruction.

FIG. 5 is an explanatory diagram showing an example of a data storage state of a data memory after execution of an instruction.

FIG. 6 is a flowchart showing a procedure of an instruction operation process in a conventional slave processor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Master processor 11 Decoding part (decoding means) 12 Operand analyzing part 12a Address calculating part (address calculating means) 12b Data fetching part 13 Master calculating part 14 Interface part (interface means) 14a Address register (address storing means) 14b Interface controller ( Access control means) 2 slave processor 21 slave operation unit 3 user program memory 4 data memory

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G05B 19/04-19/05

Claims (2)

(57) [Claims] 1. Each instruction is a master processor.SessaOr
Multiprocessor that is executed by a slave processor
A master processor, wherein the master processor analyzes the instruction and the instruction is transmitted to the master processor.
Is executed or executed on the slave processor side.
Is performed, and based on the result of the
Calculation instructions to the
Output the instruction and output the operand of the instruction
Decoding means; and an address based on the operand from the decoding means.
Address calculating means for calculatingAn address for storing the address calculated by the address calculation means.
Address storage means, data port to slave processor side
And increment data ports,
An action that controls access of the slave operation means to data
Access control means Interface means for performing
On the other hand, the slave processor receives the calculation instruction from the decoding unit and
Access to the source means, and
Slave function that reads and executes the data at the stored address
Equipped with arithmetic meansAnd When the slave operation means accesses the above data port
In this case, the data indicated by the address
To the increment data port
When accessed, the above-mentioned address is
Direct access to the data indicated by the
Increment the address stored in the dress storage means
Tried to do Multiprocessor operation characterized by the following:
apparatus. 2. The multiprocessor arithmetic unit according to claim 1,
A user program is executed by the device.
Programmable controller.