JP3457535B2 - Communication device between processors - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication device in a loosely coupled multiprocessor system. 2. Description of the Related Art In a loosely coupled multiprocessor system in which a plurality of processors and a main memory shared by the processors are connected via a system bus, communication between processors has conventionally been performed by a communication source processor. The message is stored in the above-mentioned inter-processor communication area, the source processor issues an inter-processor communication interrupt request to the destination processor, and the source processor retrieves the message from the inter-processor communication area on the main memory. I have. However, in the above-described conventional inter-processor communication method, when the communication-source processor stores a message in the inter-processor communication area on the main memory, the communication-source processor sets the communication-destination processor. Issue the inter-processor communication interrupt request, and when the communication destination processor retrieves a message from the inter-processor communication area on the main memory, the system accesses the system bus, thereby deteriorating the performance of the system. . [0004] It is an object of the present invention to provide an inter-processor communication device in which the system performance is improved by reducing the number of times of accessing the system bus. [0005] An inter-processor communication device according to the present invention comprises a plurality of processors (1, 2) and a main memory (3).
Are connected via the system bus (4) ,
Command, the processor that issued the message
The processor for the processor that issues the message in main memory
The message is stored in the communication area between Sessa (12, 13).
Each processor in a loosely coupled multiprocessor system
An inter-processor communication device provided in the processor,
The system bus that the issuing processor sends to the system bus
Command includes a data part (57) which is a message,
Specify an instruction including a write instruction to the inter-processor communication area
Command part (55) to execute
Address that specifies the interprocessor communication area for the
Section (56) and the processor information section that issued the message
(58), wherein the inter-processor communication device is a system.
A command generation unit (6) for generating a bus command;
Sends the generated system bus command to the system bus
Command transmission register (5) held for
Receives each system bus command sent on the system bus
Command reception register (50)
Each system bus command captured by the
A command address analysis unit (7) for analyzing,
Message from the data section (57) in the
Data buffer (8) and command address
The data from the data buffer (8) is controlled by the analysis unit (7).
Message and fetch the message between processors based on the message.
An inter-processor communication execution unit (9) for executing communication processing;
Built-in cache (1) that stores a part of data in main memory
1) and a key for registering and invalidating the internal cache
A cache control unit (10), and
The analysis unit (7) takes in the command reception register (50).
Of the command part (55) of each system bus command
A first comparator (51) for comparing whether or not the content is a write instruction;
And the contents of the address part (56) are
Whether the address specifies the communication area between processors
A second comparator (52) for comparing the
If the contents of the processor information section (58) are
A third comparator (53) for comparing whether or not the
When all three comparators are positive
Causes the interprocessor communication execution unit to perform interprocessor communication.
And a logic unit for generating an output for the message .
A system bus command indicating a write command to store the message in the inter-processor communication area
Communication device between other processors when running
Therefore, the inter- processor communication device of the processor to which the inter- processor communication is issued issues a command address.
Since the address analysis unit can recognize that it is communication between processors to its own processor,
Processor interrupt request from the issuing processor
Has been requested, and the issuing processor
The inter-processor communication device performs inter-processor communication processing. [0008] The inter-processor communication device according to the present invention employs a configuration in which the act of storing a message in the inter-processor communication area on the main memory is directly used as an inter-processor communication interrupt request. By doing so, the speed of inter-processor communication is increased, and the performance of the system is increased by lowering the usage rate of the system bus. Next, an embodiment of the present invention will be described. In the inter-processor communication device according to the present invention, a plurality of processors (1, 2) and a main memory (3) are connected to a system bus.
(4) connected using a system bus command
The message issuing processor sends the message in main memory.
Processor inter-processor communication area
A , provided in each processor in the loosely coupled multiprocessor system storing the message in (12, 13) .
A inter-processor communication device, the issuing processor
The system bus commands sent by the
Data part (57), which is a message, and communication between processors
Command section that specifies an instruction including an instruction to write to the area
(55), and a message
Address part (56) for specifying communication area between processors
Message processor information part (58)
And the interprocessor communication device is a system bus command.
A command generation unit (6) for generating a command;
Held for sending system bus commands to the system bus
Command transmission register (5)
Receives and captures each system bus command sent
Command reception register (50) and command reception register
Command to analyze each system bus command
Command address analysis unit (7) and in the command reception register
For taking in messages from the data section (57)
Data buffer (8) and command address analyzer (7)
Message from the data buffer (8)
And execute inter-processor communication processing based on the message.
To execute the inter-processor communication execution unit (9) and the data in the main memory.
A built-in cache (11) that stores part of the data
Cache control unit that performs cache registration and invalidation processing
(10), and the command address analysis unit (7) includes:
Each system loaded into the command reception register (50)
Command is the write command
A first comparator (51) for comparing whether or not the address
The content of (56) indicates that the communication between processors is
No. to compare whether or not the address specifies the communication area
2 and the issuer processor information section (5).
8) Whether the content is a processor other than the own processor
And a third comparator (53) for comparing the three ratios.
Processor when all comparator comparison results are positive
To make inter-processor communication unit perform inter-processor communication
The processor that issues the message issues a write instruction to store the message in the inter-processor communication area for the issuer processor on the main memory.
The system bus command shown is when the
To another processor's interprocessor communication device
The processor to which interprocessor communication is issued.
Inter-processor communication device , the command address analysis unit
Since it is possible to recognize that the communication is between processors to its own processor, the source
A request equivalent to the interprocessor communication interrupt request from the processor
Between the processors of the issuing processor.
The communication device performs an inter-processor communication process. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a loosely coupled multiprocessor system to which the present invention is applied.
And the main memory 3 are connected by a system bus 4. The main memory 3 is shared by the processors 1 and 2, and each of the processors 1 and 2 has a built-in cache memory. FIG. 1 is a block diagram showing details of a processor communication processing unit of the processors 1 and 2 in FIG.
A command generator 6 for generating an instruction (system bus command) for performing an exchange (load / store of the main memory) between the processors 1 and 2 and the main memory 3 or between the processor 1 and the processor 2; The command transmission register 5 that holds the command for sending the command to the system bus 4, the command reception register 50 that receives and holds the system bus command on the system bus 4, and the system command that the command reception register 50 holds are analyzed. A command address analysis unit 7, a data buffer 8 for taking in a message from a data portion in the command reception register 50, an inter-processor communication execution unit 9 for executing inter-processor communication under the control of the command address analysis unit 7, and a main memory Built-in cache that stores a part of data as a copy It has a 11, and a cache control unit 10 for performing registration and invalidation processing of the internal cache 11. FIG. 3 shows a layout of an inter-processor communication area provided in the main memory 3. An area 12 stores a message when the processor 1 performs inter-processor communication with the processor 2, and an area 13 stores a message for the processor 2. Stores a message when the processor 1 performs interprocessor communication. FIG. 4 shows details of a system bus command. A command section 55 for designating a command including a write instruction, an address section 56 for designating an inter-processor communication area 12 or 13 for a processor to which a message is to be issued. , A data section 57 forming a message, and a processor information section 58 that issues a system bus command.
The inter-processor communication area (see FIG. 3) is
Department is assigned. The address section 56 (see FIG. 4)
When pointing to the communication area between the processors (see FIG. 3),
The data section (see FIG. 4) is located within the communication area between the processors.
It is written to the area specified by the address part. FIG. 5 shows the relationship between the command reception register 50, the command address analysis unit 7, and the data buffer 8. The command address analysis unit 7 includes a command unit 55
First comparator 5 for comparing whether or not the command is a write command
1, a second comparator 52 for comparing whether or not the address of the address section 56 specifies an inter-processor communication area for the own processor, and a third comparator 53 for comparing that the issue source 58 is not the own processor. And The data section 57 is input to the data buffer 8, and the logical product output of each output of the first comparator 51, the second comparator 52, and the third comparator 53 and the output of the data buffer 8 are transmitted between processors. Input to the execution unit 9. Therefore, when the command is a write command, the address is an inter-processor communication area for the own processor, and the issuing source is not the own processor, the result is transmitted to the inter-processor communication execution unit 9. The data buffer 8 has a small data width on the system bus 4 despite the presence of the command reception register 50, and when a message that cannot be accommodated in the data section 57 is communicated a plurality of times, the Store the message. Next, the operation of the inter-processor communication device configured as described above will be described. Processor 1
When performing the inter-processor communication from the processor 1 to the processor 2, the processor 1 performs an operation of writing the inter-processor communication message in the area 12. Then, the system bus command generation unit 6 generates a system bus command unit including a command as a write instruction, an address as an address of the area 12, data as an inter-processor communication message, an issuer as a processor 1, and an issuer as a main memory 3. Put on the system bus 4. When the address of the area 12 is registered in the internal cache 11, the cache control unit 10 performs the registration processing of the internal cache 11. When the system bus command is taken into the command receiving register 50 of the processor 2 and the command address analysis unit 7 determines that the command is a write command, the address is the address of the area 12, and the issuing source is not the processor 2, It causes the interprocessor communication processing section 9 to perform interprocessor communication processing. FIG. 6 is a flowchart showing this processing. At the same time, the message of the data section 57 in the system bus command is stored in the data buffer 8.
The interprocessor communication processing unit 9 performs processing based on the interprocessor communication message in the data buffer 8. When the address of the area 12 is registered in the internal cache 11, the cache control unit 10
Perform invalidation processing. According to the present invention, when a system bus command issued by a communication source processor is put on a system bus, a communication destination processor fetches the system bus command, and a command address analysis unit sends the processor address to the processor itself. The source processor does not need to issue an inter-processor communication interrupt request to the destination processor again, and the usage rate of the system bus is reduced by that amount. Can be realized, and the system performance can be improved. Further, by providing a data buffer, a message exists in its own processor, so that the communication destination processor does not need to fetch the message to the main memory, so that the usage rate of the system bus is further reduced. There is an effect of doing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a loosely coupled multiprocessor system to which the present invention is applied. FIG. 3 is a diagram showing a layout of a communication area between processors in the present invention. FIG. 4 is a diagram showing a format of a system bus command according to the present invention. FIG. 5 is a diagram showing a relationship between a command reception register, a command address analysis unit, and a data buffer 8 according to the present invention. FIG. 6 is a flowchart of a command address analysis unit according to the present invention. [Description of Signs] 1, 2 processor 3 main memory 4 system bus 5 command transmission register 6 command generation unit 7 command address analysis unit 8 data buffer 9 interprocessor communication execution unit 10 cache control unit 11 internal cache 12, 13 area 50 command Receive register 51 First comparator 52 Second comparator 53 Third comparator 55 Command section 56 Address section 57 Data section 58 Publisher

Claims (1)

(57) [Claims] 1. A plurality of processors(1,2)And main memory
(3)And the system bus(4)Connected viaCis
Using the system bus command,Message issuing process
Is in main memoryTo the processor that issued the message
ToCommunication area between processors(12,13)ToTheMessage
StoreToIn loosely coupled multiprocessor systems
To, Provided for each processorIn an inter-processor communication device
So, A system that the issuer processor sends to the system bus.
The stem bus command is Data part that is the message(57)When, An instruction including a write instruction to the inter-processor communication area;
Command part to specify(55)When, The program for the processor to which the message is issued.
Address part that specifies the communication area between the processors(56)
When, The issuer processor information section of the message(58)
Consisting of SaidCommunication device between processorsIs A command generation unit for generating the system bus command
(6)When, The generated system bus command is sent to the system bus.
Command transmission register retained for transmission(5)
When, On the system busEach sent toSystem bus command
Receiving the codetake inCommand reception register(50)
When, The command reception register isEach capturedsystembus
Command address analysis unit that analyzes commands(7)When, Data part in the command reception register(57)Before
Data buffer to capture message(8)
When, The command address analysis unit(7)Controlled bySaid de
Message from the data buffer (8)
Based on sageCommunication between processorsprocessingThe processor that runs
Communication execution unit(9)When, Internal cache for storing a part of the data in the main memory
(11)When, A cache for registering and invalidating the internal cache
Control unit(10)And The command address analysis unit(7)Is The command reception register(50)ToEach capturedShi
StembusCommand part of commandContents of (55)Is written
First comparator for comparing instructions(51)When, Address sectionContents of (56)Is for the own processor
Specify the communication area between processorsAddressno
A second comparator for comparing(52)When, PublisherContents of processor information section (58)Is its own processor
Other thanProcessorA third comparator for comparing whether or not
(53) and,Comparison of the three comparators ResultsallWhen is positive
The inter-processor communication execution unitCommunication between processors
Logic unit that generates the output, The processor that issued the message is in main memoryIssuing professional
Against SessaThe message appears in the communication area between the processors.
StoreThe system bus command indicating the write command is
The processor of another processor when it gets on the system bus
Inter-communication device,Of interprocessor communication
Issuing processorCommunication device between processorsIsKo
By the command address analyzerSelfProcessorProfessional against
Communication between SessaCan be recognized,
Said processor from the issuing processor to the processor
Issued a request equivalent to the inter-communication interrupt request
The interprocessor communication device of the destination processor isProcessor
Communication between processors characterized by performing inter-communication processing
apparatus.