JPH01106158A - Control system for inter-processor data communication - Google Patents

Abstract

PURPOSE:To instantaneously fetch data when the data on one of two CPUs is required by transmitting data from the other CPU before the data on a first CPU is required and storing the received data. CONSTITUTION:A CPU 2 writes data to a data register 9 regardless of the state of the flag of a conditional register 7. In the case, a fact that an address 2 is set at a low level is stored in the register 7 in the form of a data fetching permission flag. A CPU 1 starts to monitor said permission flag of the register 7 when the data is required for processing and then fetches the data from the register 9 after detecting the fact that the permission flag is set at a low level. At the same time, the data fetching flag of the register 7 is set at a high level owing to the data fetched from the register 9. Thus the data communication is through with a 1st byte.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data communication control system between processors,
In particular, the present invention relates to a data communication control method between processors suitable for use in computers employing a multi-CPU method.

[Conventional technology]

In the conventional communication control method, when data communication is performed using the handshake processing procedure shown in FIG. It was sending out data quickly. Note that related devices of this type include, for example, Japanese Patent Publication No. 11876/1983.

[Problem that the invention seeks to solve]

In the above conventional technology, in response to a data request from one CPU, the processing of one CPU is stopped until the other CPU prepares and sends the data, as shown in the time chart of FIG. There were problems that resulted in decreased efficiency and increased processing time. Furthermore, when the data sending CPU is in the middle of other processing, the condition data cannot be sent immediately, so it is necessary to wait until the processing is finished, resulting in a large loss of time. ,
This was a problem in high-speed processing.

An object of the present invention is to provide an inter-processor data communication control system that shortens the CPU processing stop time from the output of a data request to the data reception by adding an inexpensive and simple circuit.

[Means for solving problems]

As shown in FIG. 1, the above purpose is to provide a means 10 for detecting a data acquisition operation of one CPU, and a means for generating a data request signal by the data acquisition operation and inputting it to a register 12 monitored by the other CPU. This is achieved by having the other CPU send data before one CPU requests data, and storing the data in the register 13.

[Effect]

Conventionally, when data is requested from one CPU in communication between CPUs where the data reading order is determined, the other CPU
It was necessary to expand until the processing of U was completed. In the present invention, the CPU
A register is provided between them, and by detecting the completion of the read operation of one CPU and generating a next data sending request, the other CPU sends the data from the data sending request number to the register and temporarily stores it. As a result, before a data request is made from one CPU, the other CPU outputs the data first and inputs the data to the read register of one CPU0J. As a result, when one CPU requests data, data can be taken in immediately since the data is stored in the register.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to FIG. 3 and the fifth factor.

No. 31, as an embodiment of the present invention, from CPU2 to CPU
FIG. 5 is a circuit schematic diagram showing a case where one data communication is performed, and FIG. 5 shows a data communication time chart by handshake processing of the present invention.

Next, data communication from CPU 2 to CPU 1 will be explained in this embodiment of the present invention.

In FIG. 3, the address decoding circuit 4 includes a CPU 1
The condition data register 6 is a temporary storage circuit for enabling the CPU 2 to monitor the output signal of the address decoding circuit 4, and the data register 9 is a circuit that generates a signal that becomes the Low level during the data acquisition period.
The condition data register 7, which is a temporary storage circuit for 1-byte data that can be written from U2 and readable from the CPU 1, indicates a circuit for monitoring condition data from the CPU 2 by the CPU 1, respectively. Note that the condition data register 6.7 has a data transmission request flag and a data import permission flag.

At the start of processing, the CPU 2 addresses the data register 9 and writes data regardless of the state of the flag in the condition register 7. In this write, the fact that address 2 has become OW level is stored in the condition data register 7 as a data import permission flag. CPU1 is
Processing (when data is needed, start monitoring the data import permission flag of condition data register 7,
When detecting that the flag has become low, data is taken from the data register 9. Furthermore, the data acquisition flag of the condition data register 7 becomes a low level (by the data acquisition from the data register 9). With the above steps, the first byte data communication is completed.

From the second byte, the fact that the address 4 signal output from the address decoding circuit 4 is at a low level of 7 when data is taken in from the data register 9 of the CPU 1 is stored as a data sending request flag in the condition data register 6.
This flag is monitored by the CPU 2 during the data sending process, and when it detects that the data sending request flag is at a low level, the data is committed to the data register 9. Furthermore, by writing data to the data register 9 of the CPU 2, the data sending request flag of the condition data register 6 becomes l-1.
-1i level. The subsequent procedure is the same as the first byte data communication.

When the data communication procedure explained above is shown in a time chart, as shown in FIG.
When the PUI requests data, the data from the data sending CPU, CPL 12, is already stored in the data register 9. Therefore, as shown in the general handshake process shown in FIG. C on request
Compared to issuing a data sending request to the PUI, the data waiting time from the data request for data 1 to the data reception can be shortened and the speed can be increased. Data communication from the CPU 2 to the CPU 2 can also be realized by similar processing.

〔Effect of the invention〕

According to the present invention, there is no need to output a CPU data request during CPU processing, so processing efficiency is improved by reducing the CPU processing load, and waiting time from the CPU data request output to data capture is shortened. It is possible to achieve high-speed processing using a low-cost and commercially simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the operating principle that characterizes the present invention, and FIG. 2 is a flow chart showing the procedure of handshake processing.
FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 4 is a time chart of data communication using a general handshake, and FIG. 5 is a time chart of data communication according to the present invention. 1.2', 3...CPU4,5...Address decoding circuit 6,7...Condition data register 8.9...
・Data register -0... Data fetching operation detection means 11... Data request signal generation circuit 12... Condition data register -6... Data register

Claims (1)

[Claims] 1. In data communication between a first processor and a second processor, a data register, a first condition register, and a second condition register are provided, and the first processor transmits data. The data to be output is written to the data register and a write completion flag indicating this is set in the first condition register, and when data is required, the second processor monitors the first condition register and writes there. When detecting that the completion flag is set, fetches data from the data register, simultaneously turns off the write completion flag in the first condition register, and simultaneously sets a data sending request flag in the second condition register; When the first processor monitors the second condition register and detects that the data sending request flag is set there, it writes the data to be sent to the data register, and also sets a write completion flag to that effect. is set in the first condition register, the data transmission request flag in the second condition register is turned off, and data is transferred from the first processor to the second processor in the same manner. A data communication control method between processors.