JPH01240932A - Data processor - Google Patents

Abstract

PURPOSE:To improve the execution performance of a co-processor instruction by decoding an instruction also in a co-processor simultaneously with the instruction decoding of a pipeline processing in a microprocessor (MPU). CONSTITUTION:When the MPU100 decodes the instruction, the co-processor 200 decodes the same instruction simultaneously, and when the instruction is the co-processor instruction, it is executed synchronizing with the MPU100. In such a way, a time required for command transfer and command decoding can be reduced. Also, by providing a means dedicated for the transfer of the instruction from the MPU100 to the co-processor 200, it is not required to transfer the instruction by a bus cycle, and since the co-processor instruction can be transferred precedingly in executing another instruction, no execution overhead is generated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention mainly relates to a control method for a coprocessor connected to a microprocessor (MPU), and in particular, to eliminate the overhead of command transfer from the MPU and achieve high-speed control. The present invention relates to a coprocessor control method suitable for realizing a coprocessor interface.

[Conventional technology]

Conventional microprocessors (for example, Motorola's MC68020, hereinafter referred to as MPtJ
), the instructions to the coprocessor are once sent to the MPU.
It was read, decoded, and then transferred in the form of commands using bus cycles. For details, see Motorola Inc.'s MC68881 Floating Point Coprocessor User's Manual (No.
MC68881Floating-Poj, nt C
oprocessSsor User's Manual,
1985).

[Problem to be solved by the invention]

In the conventional coprocessor, since the computing power of the coprocessor was not so high, the time n■ during command transfer was not so noticeable compared to the computing time. However, due to recent advances in LSI technology.

Although the computing power of coprocessors has improved and the computing time has become extremely short, the time for command transfer using bus cycles has not become much shorter, and as a result, the overhead of command transfer has become noticeable. It's here.

Therefore, an object of the present invention is to eliminate the above-mentioned overhead, maximize the computing power of the coprocessor, and
An object of the present invention is to provide a command transfer method for a coprocessor that can further improve processing performance.

[Means to solve the problem]

The purpose of the above is.

(]) Dedicated means for transferring commands from the MPU to the coprocessor without using bus cycles; (2) MP[
When J decodes the instruction code in advance in the pipeline, means for transferring the instruction code to the coprocessor using the above dedicated command transfer means; (3) means for transferring the above transferred instruction code to the coprocessor; (4) means for executing the processing of the decoded instructions in synchronization with the MPU.

[Effect]

MP that performs high-speed data processing by connecting a coprocessor
In U, operations inside the MPU are processed in a pipeline manner. In other words, instruction fetch.

It is divided into stages such as instruction decoding and execution, and the next instruction to be executed is processed in advance. As a result, the time required for fetching and decoding instructions is reduced, and one instruction can apparently be executed using only the time required for the execution stage.

However, when there are instructions that have to be processed by the coprocessor - the pipeline processing described above is disrupted, resulting in instruction fetch, instruction decode, and command transfer.

The processing stage is command decoding and execution. If the execution time by the coprocessor was long, the time required for command transfer and command decoding was not so much of a problem, but with advances in technology, the execution time has been shortened and command transfer is now possible.

The time required to decode commands has become a problem.

Therefore, when MPU decodes an instruction, at the same time, the coprocessor also decodes the same instruction, and if that instruction is a coprocessor instruction, Ivi I) U
By executing the command in synchronization with the command, the time required for command transfer and command decoding can be reduced.

Note that by providing a dedicated means for transferring instructions decoded by the MPU to the coprocessor.

There is no need to transfer instructions using bus cycles, and colossal instructions can be transferred in advance while other instructions are being executed, so there is no execution overhead.

〔Example〕

An embodiment of the present invention will be explained below.

FIG. 1 is a block diagram of a data processing device that is an embodiment of the present invention. The data processing device α includes a microprocessing unit (MPU) 100 and a coprocessor (CP) 20.
0 and a main memory 300, which are connected by a pass line 400. M P U i OO is a control circuit 110, an instruction register 120, and an instruction decoder] 30
and an instruction execution circuit 140. Control circuit 1
10 reads an instruction from the main memory 300 and sets it in the instruction register 20. The instruction decoder 130 decodes the instruction set in the instruction register 120 and sends the result to the instruction execution circuit 140. The instruction execution circuit 140 is
Using this decoding result, processing according to the instruction is executed.

Generally, the instruction register 120 serves as a buffer circuit between an instruction reading stage and an instruction decoding stage, and is therefore implemented as a FIFO (first in, first out) type register that can hold a plurality of instructions.

On the other hand, the coprocessor 200 includes an instruction decoder 230 and a coprocessor instruction execution circuit 240.

Instruction decoder 230 uses a dedicated instruction transfer path 250 to transfer MPU1. , OO receives an instruction to be decoded from the instruction register 120, decodes the instruction, and if the instruction is to be executed by the coprocessor, sends the decoded result to the coprocessor instruction execution circuit 2401\. Coprocessor instruction execution circuit 24.0 uses this decoding result to execute processing according to the instruction. Furthermore, M.P.
To synchronize the execution of U and the coprocessor, M
From the P TJ control circuit 110 to the MPU instruction execution circuit 1
40 and the coprocessor instruction execution circuit 240,
A next instruction execution start instruction signal 150 is output.

The MPU control circuit 110 receives a signal 160 indicating whether the instruction is to be processed by the MPU or the CP from the instruction decoder 130, and if the instruction currently being executed is an instruction to be processed by the MPU, the MPU control circuit 110 U instruction execution end signal 17
0 from the MPU instruction execution circuit 140, and in the case of an instruction to be processed by the CP, the CP instruction execution end signal 270 is received from the MPU instruction execution circuit 140.
By receiving signals from the r-' side instruction execution circuit 240, the next instruction execution start instruction signal 150 is generated.

FIG. 2 is a time chart showing the state of pipeline processing in the data processing apparatus of this embodiment. MPU 1
Since the instruction can be decoded in the coprocessor 200 at the same time as the instruction 00 is decoded, the pipeline processing of the MPU 100 is not disturbed.

FIG. 3 is a time chart when using the conventional command transfer method. Since commands are transferred to the coprocessor 200 using bus cycles, the coprocessor 200 cannot receive commands until it reaches the MPtJloo execution stage. therefore,
Thereafter, the coprocessor 200 decodes the command and starts execution, so the MPU 100 is forced to wait during this time, creating idle time for pipeline processing.

According to this embodiment, since the instruction transfer path 250 transfers the output of the instruction register 120, there is an advantage that in addition to the instruction itself, immediate data in the program can also be transferred.

In this embodiment, the instruction transfer path 250 takes out the instruction directly from the instruction register 120, but the instruction transfer path 250 takes out the instruction directly from the instruction register 120, but the instruction transfer path 250 takes out the instruction directly from the instruction register 120.
The scope of the present invention also includes the case where a compressed number of bits is transferred by the instruction transfer path 250.

Further, in this embodiment, only instructions are mainly transferred to the instruction transfer path 25.
0, but in systems where control information other than instructions (for example, information on processor status registers, etc.) is required on the coprocessor side, when the above control information is added to the instruction transfer path 250 and transferred. Also within the scope of the present invention.

Although this embodiment does not have a decoded instruction queue, in the case of an MPU that does have one, the present invention can be easily applied by having a decoded instruction queue on the CP side as well.

Furthermore, in this embodiment, a system is shown in which command decoding on the coprocessor side is completed within the time required for instruction decoding on the MPU side; If the system does not complete within the specified time, the coprocessor outputs a decoding completion report signal to the MPU control circuit, and the MPU
By waiting for this signal and starting the code for the next instruction, it is possible to easily synchronize the operations of the MPU and the coprocessor.

As described above, the coprocessor control method of the present invention can be easily implemented as in this embodiment.

〔Effect of the invention〕

As described above, according to the present invention, in a data processing apparatus that has a coprocessor outside the MPU and executes some instructions in a program by the coprocessor, the MPU
Since instructions can be decoded in the coprocessor at the same time as instructions are decoded in U's pipeline processing, it is possible to eliminate disturbances in pipeline processing, eliminate the overhead of command transfer to the coprocessor, and improve the execution performance of coprocessor instructions. It has the effect of improving

Also, compared to coprocessors that monitor the memory bus and simultaneously fetch instructions into the coprocessor when the MPU fetches them, there is no need to have a briefetch queue for instructions on the coprocessor side. Moreover, there is an effect that a control circuit for managing the briefetch queue in synchronization with the MPU becomes unnecessary.

Furthermore, in the coprocessor control method described above, MP
If a cache memory (in particular, an instruction cache) is built into the U, when a coprocessor instruction is read out from the built-in cache memory, the coprocessor will not be able to read the instruction from the memory bus. According to the present invention, since coprocessor commands can be transferred without using a memory bus, there is an effect that a high-speed coprocessor control method can be provided even in a system in which an instruction cache memory is built in the MPU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the data processing device shown in FIG. 1, and FIG. 3 is a block diagram of a data processing device according to the prior art. It is a time chart showing the operation.

Claims (1)

[Scope of Claims] 1. In a data processing device having a first processing device that mainly operates and a second processing device that operates according to instructions from the first processing device, the first processing device is a processing device that performs pipeline processing that has at least three stages: instruction fetch, instruction decode, and execution, and the first processing device performs pipeline processing that has at least three stages: instruction fetch, instruction decode, and execution.
the second processing device has means for decoding the command transferred by the second processing device, and the second processing device has means for decoding the command transferred by the second processing device; 1. A data processing device characterized by having means for executing data while synchronizing with a first processing device. 2. The command transferred by the first processing device is the instruction itself to be decoded by the first processing device, or an instruction with a flag indicating the operation mode of the first processing device added. 2. A data processing device according to claim 1. 3. The data processing according to claim 1, wherein the command transferred by the first processing device is not an instruction itself but a result of decoding the instruction by the first processing device. Device. 4. The first processing device has a FIFO (first in, first out) type register that holds a plurality of fetched instructions, takes out one instruction from the FIFO register one by one, and processes the first and second instructions. 4. The data processing device according to claim 1, wherein the data processing device decodes the data by a decoding means of the processing device. 5. The second processing device receives a next instruction execution start instruction signal from the first processing device, and determines whether the instruction decoded by the second processing device needs to be processed by the second processing device. 5. The data processing apparatus according to claim 1, wherein when the instruction is a certain instruction, processing of the instruction is started in response to the next instruction execution start instruction signal. 6. The first processing device has means for detecting that the instruction being executed is an instruction executed by the second processing device, and the second processing device has a means for detecting that the instruction being executed is an instruction executed by the second processing device. means for reporting to the first processing device that the processing of the instruction being executed by the second processing device has been completed; 6. The data processing apparatus according to claim 1, wherein the data processing apparatus issues the next instruction execution start instruction signal after waiting for an execution completion report signal from the second processing apparatus. 7. The first processing device and the second processing device are each a separate chip LSI or a separate board,
7. The data processing apparatus according to claim 1, wherein the data processing apparatus is realized by separate mounting means. 8. The data processing device according to any one of claims 1 to 7, wherein the second processing device processes command decoding and command execution in a pipeline manner. 9. The first and second processing devices operate in synchronization at each stage of instruction (command) decoding and instruction (command) execution. Data processing equipment.