JP2002351658A - Arithmetic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processor which can suppress the increase of instruction code size and enhancing arithmetic efficiency by the instruction code in a CPU, which can be efficiently used by eliminating loss of time during arithmetic processing to the utmost and which can enhance the performance as an arithmetic processing system in an extended arithmetic unit. SOLUTION: When an arithmetic result of the extended arithmetic unit 22 is read into the CPU 21, a plurality of extension instructions 82 are continuously issued to the side of the extended arithmetic unit 22 without waiting completion of all arithmetic operations by specifying an extension instruction which must be completed in the extended arithmetic unit 22 corresponding to reading of the arithmetic result by a CPU 21, obtaining the information of arithmetic operation completion corresponding to reading in the extended arithmetic unit 22 and making possible reading of an exact arithmetic result to the reading from the CPU 21 even when the extension instructions 82 are issued from the CPU 21 to the extended arithmetic unit 22 prior to the reading of arithmetic result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device comprising a CPU and an extended arithmetic unit for performing arithmetic processing in accordance with an extended instruction from the CPU.

[0002]

2. Description of the Related Art In recent years, the amount of information handled by computer systems in OA equipment, industrial equipment, and the like has increased significantly.
There has been a strong demand for speeding up the arithmetic processing performed during the information processing, and accordingly,
Many arithmetic processing devices that perform arithmetic processing as described above have been developed with an extended arithmetic unit such as a coprocessor in addition to a CPU that performs normal arithmetic, in order to speed up the processing.

[0003] Among arithmetic processing devices including such a CPU and its extended operation unit, an extended instruction is supplied from the CPU to the extended operation unit, and the extended operation unit performs an operation in parallel with the CPU according to the extended instruction. In the processing unit to perform,
When the CPU reads the operation result of the extended operation unit, a problem occurs that the operation result expected from the CPU cannot be read unless all the operation processing of the extended operation unit is completed.

[0004] As a method of coping with the above problem, a conventional technique will be described below with reference to the drawings. FIG. 9 is a conceptual diagram showing the flow of a conventional arithmetic processing system. The system is composed of a CPU (21) and an extended arithmetic unit (22).
This is a system in which an extension instruction is issued to 2). In FIG. 9, what is shown in the extended arithmetic unit (22) is C
Instructions issued from the PU (21) to the extended arithmetic unit (22), which are an extended instruction α (165) and an extended instruction β (166), and the arithmetic processing according to each instruction is executed in the extended arithmetic unit (22). Is an extended instruction to be executed.

Also, what is shown in the CPU (21) is an instruction supplied to the CPU (21), which is an extension instruction α.
(165) to the extended operation unit (22), and an extension instruction issue instruction B (163) to issue the extended instruction β (166) to the extended operation unit (22).
And an extended instruction result read instruction A (162) for reading the operation result of the extended instruction α (165), and an extended instruction β (16
Extended instruction result read instruction B for reading the operation result of 6)
(164).

Generally, an extended instruction executed by an extended arithmetic unit has a relatively long number of execution cycles. Here, it is assumed that it takes three cycles for the extension operation unit (22) to execute the extension instruction α (165) or the extension instruction β (166). That is, in a state where the extended arithmetic unit (22) is not executing the instruction, the CPU (21) executes the extended instruction issuing instruction A (161) or the extended instruction issuing instruction B (163), and then executes the extended arithmetic unit. Extended instruction α by (22)
(165) or the operation result of the extension instruction β (166)
It takes three cycles to read the instruction by executing the extended instruction result read instruction A (162) or the extended instruction result read instruction B (164).

When the number of cycles required for each operation process of the extended operation unit (22) is known as described above, according to this prior art, as shown in FIG.
Before the extended instruction result read instruction (162, 164),
NOP (instruction that is not actually processed but is used virtually to take the timing until the next instruction is executed, and can usually take the timing of one cycle) or an instruction that is not related to the operation result (for example, , A loop instruction, etc.), causing the CPU (21) to wait for the completion of the operation by the extended operation unit (22).

Another conventional technique, for example, an extended arithmetic unit (2
If the number of cycles required for each processing in 2) is not known, the CPU (21) uses the flag indicating the completion of the calculation by the extended calculator (22), and refers to the state of the flag when reading the calculation result. By judging whether or not the operation by the extended operation unit (22) is completed, the CPU
(21) waits for the completion of the operation by the extended operation unit (22).

[0009]

However, as in the above-described arithmetic processing system shown in FIG. 9, the CPU (21) executes an extended instruction result read instruction (162, 164).
If the method of inserting a NOP before the step is used, the size of the instruction code for executing the processing increases by the amount of the insertion of the NOP, and the worst case is that the number of cycles required for the operation dynamically changes. The value must be used to cause the CPU (21) to wait for the operation, which causes a problem that the processing efficiency in the operation is further reduced and the performance of the entire system is reduced.

Even when the above-mentioned completion flag is used, when a plurality of extension instructions are successively supplied from the CPU (21) to the extension operation unit (22) in advance, the completion of the operation of any extension instruction is reflected in the flag. You do not know if you are doing.
Therefore, the supply of the extended instruction from the CPU (21) to the extended computing unit (22) cannot be continuously performed in advance, and the next extended instruction is issued by the extended instruction being executed by the extended computing unit (22). It will wait for the completion of the arithmetic processing. about this,
This will be described below with reference to FIG.

FIG. 10 is a conceptual diagram showing the flow of another conventional arithmetic processing system, and shows the execution status of each instruction of the CPU (21) and the extended arithmetic unit (22). In this arithmetic processing system, as shown in FIG. 10, the CPU (21) issues an extended instruction α (165) to the extended arithmetic unit (22) by the extended instruction issuing instruction A (161), and the CPU (2)
1) refers to the extended operation unit (2) while referring to the operation completion flag.
After the completion of the operation by the extension instruction α (165) in 2), the extension instruction result read instruction A (162) is executed. After the execution of the extension instruction result read instruction A (162), the extension instruction issue instruction B ( 163), the CPU
(21) sends the extended instruction β (165) to the extended arithmetic unit (22).
Is issued.

As is apparent from FIG. 10, if this conventional technique is used, the CPU (21) cannot successively issue an extended instruction to the extended arithmetic unit (22) in a continuous manner.
U (21) and the extended arithmetic unit (22) cause a time loss, and the CPU (21) cannot efficiently use the extended arithmetic unit. This conventional technique also has a problem that the performance of the entire system is reduced. Had.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and eliminates a waiting state for completion of an operation by an extended arithmetic unit in a CPU, suppresses an increase in instruction code size, and improves operation efficiency by the instruction code. The present invention provides an arithmetic processing device capable of efficiently using the extended arithmetic unit while minimizing the time loss during the arithmetic processing and improving the performance of the arithmetic processing system.

[0014]

According to another aspect of the present invention, there is provided an arithmetic processing apparatus comprising: a CPU; and an extended arithmetic unit that performs arithmetic processing in parallel with the CPU according to an extended instruction supplied from the CPU. In the arithmetic processing device, means for adding an ID to the extended instruction supplied from the CPU to the extended arithmetic unit, and decoding of a read instruction for referring to a result of the extended instruction in the extended arithmetic unit from the CPU. Sometimes, in the read instruction,
Means for adding information indicating an extension instruction for obtaining the operation result, and means for comparing the ID added to the extension instruction with the information added to the read instruction when the CPU executes the read instruction. And a means for controlling execution of a read instruction by the CPU, wherein the control means is provided with an ID added to the extension instruction and an ID added to the read instruction as a result of the comparison at the time of execution of the read instruction. The execution of the read command is stopped until the information matches.

As described above, even when a plurality of extension instructions are issued from the CPU to the extended computing unit prior to the reading when the computation result of the extended computing unit is read to the CPU, Specifying an extension instruction that must be completed in the extended arithmetic unit in response to the reading, obtaining completion information of the operation corresponding to the read in the extended arithmetic unit, and obtaining a correct operation result for reading from the CPU side. Can be read out, a plurality of extension instructions can be issued to the extension operation unit side continuously without waiting for the end of all the operations.

[0016]

An arithmetic processing device according to claim 1 of the present invention is an arithmetic processing device comprising a CPU and an extended arithmetic unit that performs arithmetic processing in parallel with the CPU according to an extended instruction supplied from the CPU. Means for adding an ID to the extended instruction supplied from the CPU to the extended arithmetic unit, and reading the read instruction when decoding a read instruction for referring to the operation result of the extended instruction in the extended arithmetic unit from the CPU. Means for adding information indicating an extended instruction for obtaining the operation result to the instruction;
A unit for comparing the ID added to the extension instruction with information added to the read instruction when the read instruction is executed by U; and a unit for controlling execution of the read instruction by the CPU. The means is configured to stop the execution of the read command until the ID added to the extension command matches the information added to the read command as a result of the comparison at the time of executing the read command.

According to a second aspect of the present invention, there is provided the arithmetic processing unit according to the first aspect, wherein the read instruction in the arrangement order of various execution instructions of the CPU for obtaining the execution order at the time of executing the read instruction. Is disposed between the corresponding extended instruction and the next extended instruction, and as information to be added to the read instruction, means for adding the ID of the last extended instruction placed before the read instruction, Means for adding an operand indicating the number of instructions of the various execution instructions to the read instructions in the arrangement order, and executing the read instruction by executing the execution order by reducing the execution order by the number of instructions indicated by the operand. I do.

According to these configurations, when the operation result of the extended arithmetic unit is read out to the CPU side, even if a plurality of extension instructions are issued from the CPU side to the extended arithmetic unit prior to the reading, On the CPU side, an extension instruction that must be completed in the extended arithmetic unit in response to the read is specified, and completion information of the operation corresponding to the read in the extended arithmetic unit is obtained. By making it possible to read a correct operation result, a plurality of extension instructions are issued to the extension operation unit continuously without waiting for the end of all the operations.

According to a third aspect of the present invention, in the arithmetic processing unit according to the second aspect, as a result of comparison of IDs at the time of execution of the read instruction, the ID of the extended instruction for updating the arithmetic result is: I added to the executed read instruction
When the value is larger than D by one, updating of the calculation result is stopped.

According to this configuration, it is determined whether or not the operation result by the extension instruction on the extension operation unit side is read out by the CPU.
It is known before the execution of the read instruction from the PU side, and by guaranteeing that the operation result to be read cannot be rewritten by another extended instruction thereafter, for example, after issuing an extended instruction to the extended arithmetic unit, Even if the extended instruction requires a time-consuming operation before the extended instruction is executed and the operation result read instruction is executed, a plurality of extended arithmetic units are successively preceded during the processing period. Issue an instruction.

Hereinafter, an arithmetic processing unit according to an embodiment of the present invention will be specifically described with reference to the drawings.
FIG. 8 is a block diagram illustrating an outline of a system configuration using the arithmetic processing device according to the present embodiment. As shown in FIG. 8, the system configuration of this arithmetic processing device reads instructions and data arranged in a memory (24), performs operations, inputs / outputs various data, and issues extended instructions to an extended arithmetic unit (22). A memory (24) for storing instructions and data for the CPU (21) to execute various processes;
A main bus (25) for connecting the PU (21) and the memory (24), an extended arithmetic unit (22) for executing arithmetic processing based on an extended instruction issued from the CPU (21),
An extended arithmetic unit bus (23) for connecting the U (21) and the extended arithmetic unit (22). Here, the instructions arranged in the memory (24) include the extended arithmetic unit (22)
Extended instruction for CPU from CPU (21) to extended arithmetic unit (22)
Instruction to issue to the extended arithmetic unit (2
An extended instruction result read instruction for reading the operation result of the extended instruction in 2) from the extended arithmetic unit (22) by the CPU (21) is included.

In the arithmetic processing unit of the present embodiment, there is an extended instruction result read instruction that involves a delay in the execution of the processing, and a delay operation for such an extended instruction result read instruction will be described with reference to FIG. Will be described.

FIG. 5 is a conceptual diagram showing a delay operation for an extended instruction result read instruction on the CPU (21) side in the arithmetic processing unit according to the present embodiment. FIG.

Ex is an instruction to issue an extended instruction, and
“d” is an instruction for reading out the operation result of the extension instruction emitted by the extension instruction issuing instruction ex. ex and read
A, which is the first operand of the register, indicates a register to be subjected to the instruction, and 3 which is the second operand of the read,
Indicates the number of instructions that move down the execution order when executing. Other instructions A to D are instructions for executing an arbitrary process.

In this embodiment, the execution instructions of the CPU (21) are arranged in the order shown in the instruction arrangement order (141).
CPU is in line with the instruction buffer (121)
The instruction execution order according to (21) is the instruction execution order (14
The operations are performed in the order shown in 2).

Next, the execution result when the CPU (21) executes an instruction in accordance with the instruction execution order (142) of FIG. 5 will be described. First, the CPU (21) executes the extended instruction issuing instruction A (231) and issues the first extended instruction to the extended arithmetic unit (22). The extension operation unit (22) starts processing according to the issued first extension instruction based on the issued first extension instruction. However, the execution of the extension instruction by the extension arithmetic unit (22) is performed in parallel with the instruction execution of the CPU (21).

Next, the CPU (21) has a memory (24)
Read the extended instruction result read instruction A (232) from, but since the delay of three instructions is specified by the operand,
Execution of the extended instruction result read instruction A (232) is postponed.

Thereafter, the arbitrary instruction A and the extended instruction issuing instruction A (233) shown in FIG. 5 are executed. Here, the second extension instruction is further sent to the extension arithmetic unit (22). The transmitted second extended instruction starts to be executed in the extended arithmetic unit (22) as soon as the extended arithmetic unit (22) becomes able to execute the second extended instruction.

Next, the CPU (21) executes an arbitrary instruction B, and thereafter starts execution of an extended instruction result read instruction A (232) which is later executed. The operation unit (22) waits until the execution of the arithmetic processing by the first extended instruction issued by the extended instruction issuing instruction (231) is completed. However, the “completion of execution of the extended instruction result read instruction (232)” here indicates “reading of the extended instruction result”.

Thus, it is guaranteed that the register A specified by the first operand of the extended instruction result read instruction (232) contains the operation result of the first extended instruction. In short, in this embodiment,
The CPU executes the execution of the extended instruction result read instruction A (232) by the first extended instruction issuance instruction A (231) arranged last in the instructions arranged earlier. By waiting for the completion of the extension instruction, it is guaranteed that the result of the extension instruction issued by the extension instruction issue instruction A (231) can be read.

The CPU (21) can execute the extended instruction result read instruction A (232) with a delay, and by delaying the execution in this manner, the CPU (21) can execute the extended instruction result read instruction (232) and thereafter. The placed extended instruction issuing instruction A (233) can be executed first.

As a result, the CPU (21) sends the extended instruction result read instruction A (2) to the extended arithmetic unit (22).
32) Multiple extended instructions can be issued earlier than
Further, even when a plurality of extension instructions are issued prior to the extension instruction result read instruction A (232), a correct extension instruction result can be read when the extension instruction result is read.

When the user creates a program as shown in the instruction arrangement order (141) of FIG. 5 using the arithmetic processing unit of the present embodiment, first, the user executes the instruction execution order (142) of FIG. Then, the compiler rearranges the instructions in the order shown in the instruction arrangement order (141) by the compiler, and delays necessary for the arrangement of the extended instruction result read instruction A (232) in the instruction execution order (142). And the instruction arrangement order (141)
, The value of the second operand is determined and added to the extended instruction result read instruction A (232).

Next, the configuration and operation of each circuit in the arithmetic processing unit according to the present embodiment will be described. Hereinafter, a “read command”, unless otherwise noted, refers to a “read command for reading the result of an extended command”.

FIG. 1 is a block diagram showing the overall configuration of the arithmetic processing unit according to the present embodiment.
1 shows a schematic configuration of an execution unit of the extension arithmetic unit (22). However, for the sake of simplicity, only parts relating to the features of the present invention are shown. Further, in the arithmetic processing device according to the present embodiment, there is no description regarding the clock,
It is assumed that it operates in synchronization with a clock in the same manner as a normal clock-synchronous arithmetic processing device.

The CPU (21) includes an instruction buffer (121) for storing instructions fetched from the memory (24),
The read instruction (134) without delay read from the read instruction buffer (124) or the instruction buffer (12).
The instruction selector (1) selects one of the instructions (131) read out from (1) and sends it to the instruction pipeline (71).
22), an instruction pipeline (71) for decoding and executing the instruction (132) supplied from the instruction selector (122), and a read instruction buffer (133) for temporarily storing a read instruction with a delay (133). 124) and the extended instruction (82) issued by the extended instruction
D, an extended instruction ID assigning circuit (31) for outputting an extended instruction with ID (201), a delay completion ID buffer (185) for holding an ID of a read instruction waiting to be executed,
The CPU-side instruction ID comparator (35) for comparing the read instruction ID (62) with the completed instruction ID (54) which is the ID of the instruction completed by the extended arithmetic unit, and stopping the instruction pipeline (71) if necessary. Is provided.

The extension operation unit (22) is provided with an extension instruction I
An extension instruction buffer (37) for storing an extension instruction with ID output from the D assignment circuit (31), and an operation for reading an extension instruction (85) from the extension instruction buffer (37) and performing an operation according to the extension instruction (85) A register file (74) that stores the result of the circuit (73), the arithmetic circuit (73), and supplies a value required for the operation; and an extension of the extension instruction that finally writes the value to the register file (74). Instruction I
D (87) holding a complete instruction ID holding register (3
6), a read command ID (62) output from the delay completion ID buffer (185) and a valid flag (151),
And an extension operation unit that locks the operation circuit (73) if necessary, based on the value of the write extension instruction ID (112), which is the ID of the extension instruction immediately before writing the operation result in the register file output from the operation circuit (73). Side instruction ID comparator (101).

The CPU (21) in FIG.
The instruction supplied from the instruction decode stage (123)
If the decoded instruction is an extended instruction for the extended operation unit (22) after the decoding, the extended instruction issue notification (81) and the extended instruction (82) are sent to the extended instruction ID assigning circuit (31). .

As shown in FIG. 4, the extension instruction ID assigning circuit (31) has an extension instruction ID holding register (32) for holding the extension instruction ID (53) and an extension instruction issue notification (81). ALU that outputs a value obtained by incrementing the value of the extended instruction ID holding register (32)
(191) and the output of the ALU (191) is selected when there is an extension instruction issue notice (81), and when there is no extension instruction issue notice (81), the extension instruction ID holding register (3) is selected.
And a multiplexer (192) for selecting the value of 2).

Upon receiving the extension instruction issue notification (81), the extension instruction ID assigning circuit (31) increments the contents of the internal extension instruction ID holding register (32) and reads the incremented extension instruction ID (53). It is transmitted to the instruction buffer (124). In addition, the extension instruction issue notification (2
02) and an extended instruction with ID (201) obtained by adding the extended instruction ID (53) to the extended instruction (82) is sent to the extended instruction buffer (37).

ID sent to extended instruction buffer (37)
As shown in FIG. 6, the extended instruction (201) with the extension is stored in the extended instruction buffer (37) together with both the extended instruction ID and the extended instruction.
Then, the extended instruction (85) to which the extended instruction ID is added is supplied to the arithmetic circuit (73).

The arithmetic circuit (73) is connected to the register file (74) via the register file access bus (86).
Perform an operation to change the contents of Register file (7
Extended instruction ID added to extended instruction that changed 4)
(87) is stored in the completion instruction ID holding register (36).

The instruction pipeline (71) shown in FIG. 1 includes an instruction selector (1) at the instruction decode stage (123).
After decoding the instruction (132) supplied from (22), the decoded instruction (133) is added to the extended arithmetic unit (2).
If the read instruction involves a delay for reading the result of the extended instruction for 2), the read instruction buffer (12
4) Read command with delay and its delay amount (13
3) to invalidate the read instruction with the decoded delay.

The read command buffer (124) is a first-in first-out buffer, and the read command buffer (124) to which the read command with delay and the delay amount (133) are sent is, as shown in FIG. The read command with delay and the delay amount (133) are stored in (124).

At this time, the extended instruction ID (53) is added to the read instruction and stored by referring to the extended instruction ID holding register (32) in FIG. And the extended instruction issued by the extended instruction issuing instruction arranged at the end of the instructions.

Upon receiving the instruction supply notification (137) from the instruction selector (122), the read instruction buffer (124) decrements all delay amounts buffered in the read instruction buffer (124). As a result of the decrement, when the delay amount of the first read instruction becomes 0, the first read instruction is supplied to the instruction selector (122) as a read instruction (134) without delay, and is added to the instruction. The completed ID is used as the delay completion instruction ID (135) and the delay completion ID buffer (185)
Send to The delay completion ID buffer (185) is a first-in first-out buffer, and is a read instruction buffer (12).
The delay completion command ID (135) sent from 4) is stored.

The delay completion ID buffer (185) includes a read instruction ID holding register (34), and reads out the stored oldest delay completion instruction ID from the stored instruction ID (6).
As 2), it is stored in the read command ID holding register (34). When the read instruction execution notification (139) sent from the instruction pipeline (71) is received, the oldest delayed completion instruction ID in the buffer is deleted, and the oldest delayed completed instruction ID among the remaining delayed completed instruction IDs is deleted. The read instruction ID holding register (34) is updated with the value of the completed instruction ID.

The read command ID (62) held in the read command ID holding register (34) by the delay completion ID buffer (185) is added to the next read command executed in the CPU (21). ID.
However, the delay completion ID buffer (185) has a valid flag (151) and the delay completion ID buffer (185).
Is empty, the valid flag (151) becomes 0, and a meaningless value enters the read command ID. Also, delay completion ID
If the buffer (185) is not empty, the valid flag (1
51) becomes 1.

The instruction ID comparator (35) on the CPU side in FIG.
Is a delay completion ID buffer (18) as shown in FIG.
5) Read instruction ID (62), which is the content of read instruction ID holding register (34), and completion instruction ID
Completion instruction ID (5) which is the content of the holding register (36)
4) are compared, and if both are equal, 1 is output; otherwise, 0 is output.
An AND circuit (211) which takes the logical product of the output of (212) and the valid flag (151) in the delay completion ID buffer (185), and an instruction ID mismatch flag (84) holding the value.

The instruction ID mismatch flag (84) in the instruction ID comparator (35) on the CPU side indicates that the ALU (21
Due to 2) and the function of the AND circuit (211), the read command ID (62), which is the ID added to the read command to be executed next by the CPU (21), and the extended arithmetic unit (22) Becomes 1 when the completed instruction ID added to the most recently completed extended instruction matches the completed instruction ID,
Otherwise, it is 0.

When the instruction pipeline (71) executes the read instruction referring to the calculation result of the extension instruction and reads the operation result of the extension instruction from the register file (74), the instruction ID comparator (35) in the CPU side. The instruction ID mismatch flag (8) is referred to by referring to the instruction ID mismatch flag (84).
If 4) is 1, the instruction pipeline (71) is locked, and the execution of the read instruction is stopped by the instruction ID mismatch flag (8).
4) Wait until the value becomes 0.

After waiting for the execution of the read instruction until the instruction ID mismatch flag (84) becomes 0, or when the instruction ID mismatch flag (84) is originally 0, the extension instruction is sent via the register file access bus (83). Is read from the register file (74), and the execution of the read command is continued.

By this operation, when executing the read command,
Completion of the associated extended instruction is guaranteed, and the operation result of the correct extended instruction can be obtained. Next, the operation of the instruction selector (122) will be described.

The instruction selector (122) of FIG. 1 reads the normal instruction (131) from the instruction buffer (121) when the read instruction (134) without delay is not supplied from the read instruction buffer (124). , As an instruction (132) to the instruction pipeline (71),
When the read instruction (134) without delay is supplied from the read instruction buffer (124), the read instruction (134) without delay is supplied to the instruction pipeline (71) as the instruction (132). In each case, the instruction (132) is stored in the instruction pipeline (7).
When the instruction is supplied to 1), an instruction supply notification (137) is sent to the read instruction buffer (124).

By the operation of the instruction selector (122), the delayed read instruction is transferred to the instruction buffer (12).
An instruction (131) supplied from 1) can be interrupted and sent to the instruction pipeline (71).

The above-described instruction selector (122), read instruction buffer (124), instruction pipeline (71)
Operation, the execution of the read instruction can be delayed, and by delaying the execution of the read instruction, the read instruction and the extended instruction located at the rear end of the instructions located before the read instruction are delayed. After associating the issued instruction, another extended instruction can be issued before executing the read instruction.

Next, before the CPU (21) reads the operation result from the extended operation unit (22) by the read instruction, the operation result is prevented from being changed by another extension instruction different from the corresponding extension instruction. Here's how.

The operation circuit (73) converts the write extension instruction ID (112), which is the ID of the extension instruction immediately before writing the operation result into the register file (74), into the extension operation unit side instruction ID comparator (101) of FIG. ).

This extended operation unit side instruction ID comparator (10
1) are the read instruction ID (62) and the write extended instruction ID (1) which are the contents of the read instruction ID holding register (34) in the delay completion ID buffer (185) shown in FIG.
12), an ALU (214) that outputs 1 when the write extension instruction ID (112) is larger by 1 and otherwise outputs 0, an output of the ALU (214) and a delay completion ID buffer ( 185) (15)
An AND circuit (213) for performing a logical AND operation with 1) and a write inhibit flag (113) for holding the AND circuit are provided.

The write inhibit flag (113) in the instruction ID comparator (101) on the extended computing unit side is
Due to (214) and the function of the AND circuit (213), the write extended instruction ID (112), which is the ID of the extended instruction immediately before the operation result is written into the register file (74) and the validity flag is 1, becomes the CPU (21). A read instruction ID which is an ID added to a read instruction executed next.
1 if greater than (62), 0 otherwise
Becomes

When the operation circuit (73) stores the operation result of the extension command in the register file (74), the operation circuit (73) refers to the write inhibit flag (113). 73) is locked, and the execution of the extension instruction is made to wait until the write inhibit flag (113) becomes 0. Write inhibit flag (113)
After the execution of the extension instruction is waited until the value of the extension instruction becomes 0, or when the write inhibit flag (113) is originally 0, the operation result of the extension instruction is transferred to the register file (74) via the register file access bus (86). Write to
Continue execution of extension instructions.

According to this operation, it is possible to prevent the operation result from being changed by an extension instruction different from the corresponding extension instruction before the read instruction reads the operation result.

[0063]

As described above, according to the present invention, when the operation result of the extended operation unit is read to the CPU, a plurality of extension instructions are issued from the CPU to the extended operation unit prior to the reading. Even if it has been performed, the CPU side specifies an extension instruction that must be completed in the extended arithmetic unit in response to the reading, obtains the completion information of the operation corresponding to the read in the extended arithmetic unit, and By reading the correct operation result in response to the read operation from the CPU, it is possible to continuously issue a plurality of extension instructions to the extension operation unit without waiting for the end of all the operations.

Further, it is known before the execution of the read instruction from the CPU whether or not the operation result by the extension instruction on the extension operation unit side is read out by the CPU, and the operation result to be read is obtained by another extension instruction after that. For example, after an extended instruction is issued to an extended arithmetic unit, it takes time to execute the extended instruction and execute an instruction to read out the operation result. Is required, a plurality of instructions can be issued successively to the extended arithmetic unit during the processing period.

As described above, in the CPU, the waiting state of the completion of the operation by the extended arithmetic unit can be eliminated, the increase in the instruction code size can be suppressed, and the operation efficiency by the instruction code can be improved. Time loss during arithmetic processing can be minimized, and the time can be efficiently used, and the performance of the arithmetic processing system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an arithmetic processing device according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration of a CPU-side instruction ID comparator according to the embodiment;

FIG. 3 is a block diagram showing a configuration of an extended operation unit-side instruction ID comparator according to the embodiment;

FIG. 4 is a block diagram showing a configuration of an extended instruction ID assigning circuit according to the embodiment;

FIG. 5 is a conceptual diagram showing a read command delay operation in the embodiment.

FIG. 6 is a conceptual diagram showing a content structure of an extended instruction buffer according to the embodiment;

FIG. 7 is a conceptual diagram showing a relationship between a read instruction buffer and a delay completion ID buffer according to the embodiment;

FIG. 8 is a block diagram showing an outline of a system configuration of the arithmetic processing unit according to the embodiment;

FIG. 9 is a conceptual diagram showing a flow of a conventional arithmetic processing.

FIG. 10 is a conceptual diagram showing a flow of another conventional arithmetic processing.

[Explanation of symbols]

 21 CPU 22 Extended arithmetic unit 23 Extended arithmetic unit bus 24 Memory 25 Main bus 31 Extended instruction ID assignment circuit 32 Extended instruction ID holding register 34 Read instruction ID holding register 35 CPU side instruction ID comparator 36 Completed instruction ID holding register 37 Extended instruction Buffer 53 Extended instruction ID 54 Completion instruction ID 62 Read instruction ID 71 Instruction pipeline 73 Arithmetic circuit 74 Register file 81 Extended instruction issue notification 82 Extended instruction 83 Register file access bus 84 Instruction ID mismatch flag 85 Extended instruction 86 Register file access bus 87 Extended instruction ID 101 Extended operation unit side instruction ID comparator 112 Write extended instruction ID 113 Write inhibit flag 121 Instruction buffer 122 Instruction selector 123 Instruction decode stage 12 Read instruction buffer 131 Instruction 132 Instruction 133 Read instruction with delay and delay amount 134 Read instruction without delay 135 Delay complete instruction ID 137 Instruction supply notification 139 Read instruction execution notification 141 Instruction placement order 142 Instruction execution order 151 Valid flag 161 Extension Instruction issue instruction A 162 Extended result read instruction A 163 Extended instruction issue instruction B 164 Extended result read instruction B 165 Extended instruction α 166 Extended instruction β 185 Delay completion ID buffer 191 ALU 192 Multiplexer 201 Extended instruction with ID 202 Extended instruction issue notification 211 AND circuit 212 ALU 213 AND circuit 214 ALU 231 Extended instruction issue instruction 232 Extended instruction result read instruction 233 Extended instruction issue instruction

Claims (3)

[Claims] 1. An arithmetic processing device comprising a CPU and an extended arithmetic unit for performing arithmetic processing in parallel with the CPU in accordance with an extended instruction supplied from the CPU, wherein the extended instruction supplied from the CPU to the extended arithmetic unit is Means for adding an ID, and when decoding a read instruction for referring to an operation result by the extension instruction in the extension operation unit from the CPU, information indicating the extension instruction for obtaining the operation result is included in the read instruction. Means for adding, means for comparing the ID added to the extension instruction with the information added to the read instruction when the CPU executes the read instruction, and means for controlling the execution of the read instruction by the CPU. Wherein the control means is added to the extension instruction as a result of the comparison at the time of execution of the read instruction. An arithmetic processing device, wherein execution of the read command is stopped until an ID matches information added to the read command. 2. A read instruction in an arrangement order of various execution instructions of a CPU for obtaining an execution order at the time of execution of a read instruction is arranged between a corresponding extension instruction and a next extension instruction. Is added to the I of the last extended instruction placed before the read instruction.
A means for adding D and an operand indicating the number of instructions of the various execution instructions are added to the read instructions in the arrangement order, and when the read instruction is executed, the execution order is reduced by the number of instructions indicated by the operand and executed. 2. The arithmetic processing device according to claim 1, further comprising: 3. When the ID of an extended instruction for updating an operation result is larger than the ID added to the executed read instruction by a comparison of IDs at the time of execution of the read instruction, the operation result is updated. The arithmetic processing device according to claim 2, wherein the processing is stopped.