JP2001051845A - Out-of-order execution system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the process time from the generation of a predicate to conditioned execution by providing a dedicated inter-predicate operation unit which performs out-of-order execution. SOLUTION: When it is judged that operation pipe feed control logic 1010 can not execute an instruction (register 1009 is ineffective), no instruction is fed to an operation pipe. In this case, a comparator 1006 compares a rename register number enqueued an instruction queue 1004 with a rename register number generated by a predicate generation instruction execution unit 1002 and the register 1009 is made effective through an OR circuit 1008 when they match each other. Consequently, the operation pipe feed control logic 1010 feeds an instruction to the operation pipe. Source data of operation are sent out to a computing element 1011 by selecting a forwarding bus 1201 from a predicate generation instruction execution unit 1002 by a selector 1101 and operated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a conditional execution method using a predicate and a processor using the execution method.

[0002]

2. Description of the Related Art Super scalar and VLIW (Very Long)
For example, a computer that aims at instruction-level parallelism, such as Instruction Word, holds a boolean value called a predicate in the instruction as an execution condition and executes the instruction only when the predicate value is true (conditional execution).
Some have a mechanism to do so.

In this predicate, in order to generate a high-speed execution code using instruction-level scheduling or the like, a compiler includes an instruction for generating predicate data (a predicate generation instruction), and an inclusive statement between two predicate data in an execution instruction statement. Instructions that perform relational operations (inter-predicate operation instructions), instructions that perform a store operation to memory only when the predicate value is true (conditional store instructions), and registers that differ when the predicate value is true and false Generate an instruction to select a value (register selection instruction).

When a store or a register is selected based on a plurality of conditions, a true / false value of a condition is obtained by an inter-predicate operation instruction based on a plurality of predicate data generated by a predicate generation instruction, and the value is used by using the value. Execute a conditional store or register select instruction.

The processor sends the predicate data generated by the predicate generation instruction execution unit to the inter-predicate operation instruction execution unit. The inter-predicate operation instruction execution unit performs an operation in accordance with the order of instructions in the execution statement, and sends the predicate data to the conditional store instruction execution unit and the register selection instruction execution unit after the predicate value is determined. The conditional store instruction execution unit and the register selection instruction execution unit evaluate this predicate value and perform conditional execution.

FIG. 2 shows an example of a time chart of conditional execution (execution of a register selection instruction) using the conventional predicate technique.

In FIG. 2, instructions 1 to 5 are executed in the order of the execution statement.
5 shows a time chart when the five instructions are executed.
Instruction 1 is a predicate generation instruction, instructions 2 to 4 are inter-predicate operation instructions, instruction 5 is a register selection instruction, instruction 2 is the operation result of instruction 1, instruction 4 is the operation result of instructions 2 and 3, and instruction 5 is the operation result of instructions 2 and 3. The operation result of the instruction 4 is used as source data. For other predicate source data, the value of the predicate body register is used.
(Valid data exists in the predicate register when the instruction is issued.) A predicate generation instruction, an operation instruction between predicates,
It is assumed that both register selection instructions end in five cycles after the instruction is issued, and those cycles are designated as D and E, respectively.
0, E1, E2, and C stages. Issue of instructions to each instruction execution unit in the D stage, fetching of instructions to each execution unit in the E0 stage, determination of instruction input to the arithmetic unit in the E1 stage, operation in the E2 stage, and execution results in registers in the C stage Is written.

Further, it is assumed that the number of instructions that can be simultaneously processed by the predicate generation instruction execution unit, the inter-predicate operation instruction execution unit, and the register selection instruction execution unit is one, and that the pipeline processing is possible.
The operation result of the E2 stage is output between the operation unit output of the predicate generation instruction execution unit and the operation unit input of the operation instruction execution unit between predicates and between the output and input of the operation unit of the operation instruction execution unit between predicates. It is also assumed that there is a bypass to reflect this.

First, the instruction issuing unit issues the instruction 1 to the predicate generation instruction execution unit at a timing of 2000. The predicate generation instruction execution unit
Instruction 1 is fetched at the timing of 2001. Since the source data of the instruction 1 is valid, it is determined that the instruction can be executed at the timing of 2002, and an instruction execution signal is sent to the operation pipe. The operation pipe generates predicate data at the timing of 2003, and stores the generated data in the predicate register at the timing of 2004.

The operation of the instruction 2 is performed by the operation unit of the inter-predicate operation instruction execution unit at the timing of 2013 one cycle after the instruction 1. The source data of the instruction 2 generated by the instruction 1 is forwarded by using a bypass from the operation unit of the predicate generation instruction execution unit to the operation unit of the inter-predicate operation instruction execution unit. 20
In order to make it possible to determine the input of an instruction to the arithmetic unit at the timing of 12, the pre-dicated operation instruction execution unit outputs a signal indicating the instruction execution of the instruction 1 from the predicate generation instruction execution unit at the timing of 2002 and a destination register of the operation result. Receive the number.

Since the pipe of the inter-predicate operation instruction execution unit is pipelined, the operation of instruction 3 is performed at the timing of 2023, one cycle after instruction 2, and the operation of instruction 4 at the timing of 2033, one cycle after instruction 2. . The operation of the instruction 4 uses the operation results of the instructions 2 and 3 as source data. The generated data of the instruction 2 is read from the predicate register, and the generated data of the instruction 3 is read from the bypass.

The register selection instruction 5 is executed after the data generated by the instruction 4 is written into the predicate register.
At timing 043, the value is read out and the register is selected according to the predicate value.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to reduce the processing time from generation of a predicate to conditional execution.

[0014]

Means for Solving the Problems An arithmetic unit for calculating an inclusion relation between two predicates in an execution statement, which is called an operation between predicates, is separately provided, and the arithmetic unit converts predicate data generated by another arithmetic unit. The execution of conditional execution is speeded up by executing out-of-order execution while forwarding.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the out-of-order execution of an inter-predicate operation instruction according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of hardware for performing out-of-order execution of an inter-predicate operation instruction.

The instruction issuing unit 1001 issues inter-predicate operation instruction information to the inter-predicate operation instruction execution unit 1003. At this time, the instruction issuing unit 10
01 is a predicate generation instruction execution unit 1002,
Predicate generation instruction information, register selection instruction information, and conditional store instruction information may be simultaneously issued to the conditional store instruction execution unit 1015 and the register selection instruction execution unit 1016.

The issued inter-predicate operation instruction information is stored in registers 1005 and 1009 in the instruction queue 1004. The source data of the issued instruction is valid in the register 1009 via the OR circuit 1008 (the source data of the instruction is stored in the predicate name register 1012 or the predicate main register 1).
013) is stored.

When there are a plurality of source data of the inter-predicate operation instruction, there are as many registers 1009 as there are source data for each register.

When all the information stored in the instruction queue 1004 is valid in the register 1009, the operation pipe input control logic 1010 determines that the instruction can be executed and inputs the instruction to the operation pipe.

The operation pipe and the input control logic 1010 input an executable instruction among the plurality of instructions stored in the instruction queue 1004 to the operation pipe, but the input order is an execution instruction statement order (program order). You do not need to depend.

If the register 1009 is valid when the instruction is issued, the source data of the operation is stored in the predicate name register 1012 or the predicate main register 101.
3, the read path 12
02 and either of the read paths 1203, are selected by the selector 1101 and sent to the arithmetic unit 1011 for calculation.

When the operation pipe input control logic 1010 determines that the instruction cannot be executed (register 1009)
Is invalid), no instruction is input to the arithmetic unit pipe. In this case, the instruction queue 1004 waits for the operation results of the predicate generation instruction execution unit 1002 and the inter-predicate operation instruction execution unit 1003.

The rename register number waiting in the instruction queue 1004 and the rename register number generated by the predicate generation instruction execution unit 1002 are compared by the comparator 1006.
The register 1009 is made effective via the R circuit 1008. As a result, the operation pipe input control logic 1010 inputs an instruction to the operation pipe.

For the source data of the operation, the selector 1101 selects the forwarding path 1201 from the predicate generation instruction execution unit 1002, and
011 for calculation. The predicate data generated by the predicate generation instruction execution unit 1002 is stored in the predicate name register 1012.

A comparator 1007 compares the rename register number waiting in the instruction queue 1004 with the rename register number storing the operation result executed by the inter-predicate operation instruction execution unit 1003.
The coincident number enables the register 1009 via the OR circuit 1008. As a result, the operation pipe input control logic 1010 inputs an instruction to the operation pipe.

As the source data of the operation, the forwarding path 1204 of the operation result of the operation unit 1011 is set to the selector 1
The selection is made by 101 and sent to the computing unit 1011 for computation.

The operation result is stored in the predicate name register 1012.

Predicate name register 1012
And the predicate data generated by the predicate generation instruction execution unit are written back to the predicate body register 1013 by the instruction completion control unit 1014 while guaranteeing the instruction execution order.

Conditional store instruction execution unit 1015
Uses the predicate determined in the predicate body register 1013, evaluates the predicate value in the conditional store instruction execution unit 1017, and performs conditional execution by performing a store operation in the memory only when the predicate value is true.

Register selection instruction execution unit 1016
Receives the predicate name register number issued by the instruction issuing unit and the body register number,
Necessary predicate data is selected by the selector 1102, and conditional execution is performed by selecting different register values depending on whether the predicate value is true or false.

FIG. 3 is a time chart of conditional execution (execution of a register selection instruction) using a predicate according to the present invention.

By executing the same instruction example as in FIG.
Assuming that the operation result is written to the register in 5 cycles after the instruction is issued, as in
The stages are called D, E0, E1, E2, and C1 stages. Issue of instructions to each instruction execution unit in the D stage, fetching of instructions to each execution unit in the E0 stage, determination of instruction input to the operation unit in the E1 stage, E2 stage operation, and execution results in the rename register in the C1 stage Is written. Thereafter, write-back from the rename register to the main body register is performed in a cycle called C2 stage.

It has been assumed that the instruction issuing unit can issue four instructions at the same time. A predicate generation instruction execution unit, a predicate operation instruction execution unit,
The number of instructions that can be processed simultaneously by the register selection instruction execution unit is 1 and it is assumed that pipeline processing can be performed.

The instruction issuing unit sends the instruction information of instructions 1 to 4 to the predicate generation instruction execution unit and the inter-predicate operation instruction execution unit at the same timing.
000, 3010, 3020, 3030.

The predicate generation instruction execution unit is 3
The instruction information of the instruction 1 issued at the timing of 000 is 3
It takes in at the timing of 001. Since the source data of the instruction 1 is already valid when the instruction is issued, it is determined that the instruction can be executed at the timing of 3002, and an instruction execution signal is sent to the operation pipe. The operation pipe generates a predicate at the timing of 3003, and writes to the rename register at the timing of 3004. The operation result written to the predicate name register is 300
At the timing of 5, it is written back to the predicate main register.

The inter-predicate operation instruction execution unit stores the instruction information of the instructions 2, 3, and 4 issued at the timings of 3010, 3020, and 3030 as 3011, 30
21 and 3031.

The instruction 2 uses the operation result of the instruction 1 as source data, but stalls at the E0 stage because the source data is invalid when the instruction information is taken into the instruction queue. The inter-predicate operation instruction execution unit receives the instruction execution signal of instruction 1 and the predicate name register number to which the operation result is written from the predicate generation instruction execution unit at a timing of 3002,
The state of the instruction 2 is changed from the non-executable state to the executable state. It is determined that the instruction 2 can be executed at the timing of 3012, the operation is performed at the timing of 3013,
At the timing of writing to the rename register, 301
At the timing of 5, write back to the predicate main register is performed.

The instruction 3 is taken into the instruction queue of the inter-predicate operation instruction execution unit at the same time as the instruction 2.
Since the source data is valid at the time of being taken into the instruction queue, the instruction data is not stalled in the E0 stage, but overtakes the instruction 2 and is input to the arithmetic unit at the timing of 3022 (out-of-order execution). Operation is performed at the timing of 3023, and writing to the predicate name register is performed at the timing of 3024, but stalls at the C1 stage to wait for the write back (3015) of the preceding instruction 2. The write back to the predicate main register is performed at the same timing as the instruction 2 at 3025, but the in-order guarantee of the predicate main register is performed by overwriting the data of the instruction 2 with the data of the instruction 3 at the time of writing.

The instruction 4 uses the operation results of the instructions 2 and 3 as source data. Since the source data is invalid at the time of issuing the instruction, the stall is performed in the E0 stage until the two source data are both valid. In the inter-predicate operation instruction execution unit, based on the instruction execution signals of instructions 2 and 3 and the operation result writing destination predicate name register number at timings 3012 and 3022, a register indicating that the source data of instruction 4 is valid is stored. Set the value to true. As a result, the instruction 4 becomes executable at the timing of 3032, performs the operation at the timing of 3033, writes the operation result to the predicate name register at the timing of 3034, and writes back to the predicate main register at the timing of 3035. The instruction 5 is issued from the instruction issuing unit at the timing of 3040, and is taken into the instruction queue of the register selection instruction executing unit at the timing of 3041. The instruction 5 stalls at the E0 stage to wait for the operation result of the instruction 4 used as the source data. The instruction 5 is input to the arithmetic unit at the timing of 3042, the predicate value is read from the predicate name register at 3043, and the register is selected based on the value. Is performed.

[0041]

As described above, in the conventional method shown in FIG. 2, the number of cycles required from the issue of instruction 1 to the execution of instruction 5 by the instruction 5 is nine. In FIG. 3 using the present invention, a series of processing ends in eight cycles.

As described above, by providing a dedicated inter-predicate arithmetic unit for performing out-of-order execution, it is possible to improve the performance of a processor that performs conditional execution using predicates.

[Brief description of the drawings]

FIG. 1 is a configuration example of an inter-predicate operation execution unit according to the present invention.

FIG. 2 is a time chart of conventional conditional execution (execution of a register selection instruction) using a predicate.

FIG. 3 is a time chart of conditional execution (execution of a register selection instruction) using a predicate according to the present invention.

[Explanation of symbols]

1001 Instruction issuing unit, 1002 Predicate generation instruction execution unit, 1003 Inter-predicate operation instruction execution unit, 1004 Instruction queue, 100
5 ... Latch for holding instruction information, 1006 ... Rename register number comparator, 1007 ... Rename register number comparator,
1008: OR circuit, 1009: Source data valid flag holding latch, 1010: Operation pipe input control logic, 1
011: arithmetic unit, 1012: predicate name register, 1013: predicate body register, 10
14: Instruction completion control unit, 1015: Conditional store instruction execution unit, 1016: Register selection instruction execution unit, 1101: Inter-predicate operation source data selector, 1102: Register selection source data selector, 1201: Predicate generation instruction execution result bypass, 1202: Predicate name register read path, 1203: Predicate body register read path, 1204: Bypass operation result between predicates, 1205: Instruction completion control signal.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Zenya Moriyama 1-Horiyamashita, Hadano-shi, Kanagawa F-term in Hitachi Information Technology Co., Ltd. 5B013 AA12 BB04 CC10 5B033 AA14 BD00 CA22

Claims (5)

[Claims] In a computer system having a mechanism for holding an execution condition based on a boolean value called a predicate in an instruction and executing the instruction only when the predicate value is true (conditional execution), An arithmetic unit that performs a logical operation (inter-predicate operation) between a plurality of predicate values is provided separately from an arithmetic unit that generates a predicate value from a floating-point operation or an integer operation, and instructions executed by the arithmetic unit and other operations An out-of-order execution method, wherein the order of execution of instructions executed by a container does not depend on the order of instructions in an execution statement. 2. A computer system having a mechanism for holding an execution condition based on a boolean value called a predicate in a statement and executing the instruction only when the predicate value is true (conditional execution). An arithmetic unit that performs a logical operation (inter-predicate operation) between a plurality of predicate values is provided separately from an arithmetic unit that generates a predicate value from a floating-point operation or an integer operation, and instructions executed by the arithmetic unit and other operations The order of execution of instructions executed by the unit does not depend on the order of instructions in the execution statement, and the execution order among a plurality of instructions that perform operations between predicate data does not depend on the order of instructions in the execution statement. Out-of-order execution method. 3. The out-of-order execution method according to claim 1, wherein the unit for executing the inter-predicate operation instruction includes an instruction queue, an operation unit, and a register (predicate name) for temporarily holding an inter-predicate operation result. Register) and a register (predicate body register) that stores the predicate value after guaranteeing the execution instruction statement order (in-order), and a unit that issues an operation instruction between predicates is used as an operation resource for an instruction code and an operation. Predicate main body register number and predicate name register number in which predicate data (source data) is stored, flag indicating whether valid source data is stored in main body register or rename register, stored in register Issues a flag indicating whether the source data is valid or invalid.The inter-predicate operation instruction execution unit stores those operation resources in the instruction queue, and all the source data is valid when the instruction issue unit issues the operation resource. When the instruction issuing unit issues an operation resource and the source data contains an invalid instruction when the instruction issuing unit issues an operation resource, the predicate generated by the own operation unit and other operation units A transition is made to an executable state by receiving (forwarding) a rename register number in which data is stored via a bypass route, and the predicate name register and the predicate are changed from executable ones in the operation resources stored in the instruction queue. Read operation source data from main unit register An out-of-order execution method that executes an operation between predicates, stores the operation result in a temporary predicate name register, and then stores it in a predicate main register according to an instruction from an instruction completion control unit that guarantees the order of execution statements . 4. The out-of-order execution system according to claim 1, wherein the unit for executing the operation instruction between predicates is a reservation station, an arithmetic unit, and a register (predicate name) for temporarily holding an operation result between predicates. Register) and a register (predicate body register) that stores the predicate after guaranteeing the execution instruction sequence (in-order), and a unit that issues an operation instruction between predicates stores instruction codes and source data as operation resources Issue a predicate name register number, operation source predicate data, and a flag indicating whether the operation source data is valid or invalid, store those operation resources in an instruction queue called a reservation station, and If the source data is all valid at the time the row unit issues the computational resource, the state is changed to the executable state in the reservation station, and the invalid source data is deleted when the instruction issuing unit issues the computational resource. In the case of including the predicate data generated by the own operation unit and other operation units, the rename register number and the predicate data as the operation source are received (forwarding) via the bypass route (transfer) to make a transition to the executable state. Executes an operation between predicates using source data stored in the reservation station from the executable resources in the operation resources stored in the reservation station, stores the operation results in the temporary predicate name register, and then executes the execution instruction sequence. Keep An out-of-order execution method characterized by storing in a predicate body register according to an instruction from an instruction completion control unit to be verified. 5. A processor using an out-of-order execution method of an inter-predicate operation instruction according to claim 3.