JP2668987B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for increasing the speed of a computer.

2. Description of the Related Art Conventional data processing devices include, for example, Tatsumoto Motooka, "Computer System Technology," (48.4.20), Ohmsha, P93-9
Shown in 9.

FIG. 10 is a block diagram of this conventional data processing device. In FIG. 10, 11 is an instruction prefetching device for prefetching an instruction code, 12 is an instruction decoding device, 13 is an address calculation device for performing operand address calculation, 14 is an operand prefetching device for performing operand prefetching, and 15 is an arithmetic device. , 16 is an input / output bus for connecting memory, I / O, etc., 17 is an instruction prefetching device 11, an operand prefetching device 14,
And a bus controller for controlling the input / output bus 16 by arbitrating requests from the arithmetic unit 15 when writing operands.

The instruction decoding device 12 decodes the instruction code pre-read by the instruction pre-reading device 11 and provides control information related to instruction execution, and control information for operand address calculation and pre-reading when a memory operand is fetched, and memory. When writing to the address is performed, control information for calculating the address of the operand is issued to the address calculation device 13.

The address calculator 13 calculates the address of the operand, and stores the operand address, the control information associated with the memory reference, and the control information related to the instruction execution into the operand prefetcher.
Send to 14.

The operand prefetch device 14 issues a request to the bus control device 17 when fetching a memory operand is necessary, and prefetches the operand according to the operand address received from the address calculation device 13. The read-ahead data of the operand received from the bus control device 17, the write address of the operand when accompanied by writing to the memory received from the address calculation device 13, and control information on instruction execution are sent to the arithmetic device 15.

The arithmetic unit 15 executes an arithmetic operation according to the prefetch data received from the operand prefetch unit 14 and the control information relating to the instruction execution. When it is necessary to write the operation result to the memory, a request is sent to the bus control device 17 to write the operation result to the memory in accordance with the write address received from the operand prefetch device 14.

The operation of the conventional data processing apparatus configured as described above will be described below.

FIG. 11 shows an operation timing chart. The instructions executed in the instruction prefetching device 11, the instruction decoding device 12, the address calculating device 13, the operand prefetching device 14, and the arithmetic unit 15 are shown in clock units. here,
The instruction prefetching device 11 has a cache memory inside, and the required clock number of each device is such that the instruction prefetching device 11 (1 clock), the instruction decoding device 12 (1 clock), the address calculation device 13 (1 clock), the operand prefetching device. The case of 14 (3 clocks) and the arithmetic unit 15 (1 clock) is shown. The instruction sequence being executed is an instruction that does not require fetching two memory operands following an instruction that requires fetching memory operands, and is a repetition of these three instructions. Specifically, instructions 1 and 4 are instructions that require fetching of memory operands, and instructions 2, 3 and
Instructions 5 and 6 do not require fetching of memory operands. The initial state of the pipeline is empty (for example, at the time of conditional branch). Instruction 1 is prefetched by the instruction prefetching device 11 at clock t1 and issues the instruction code to the instruction decoding device 12. At the clock t2, the instruction is decoded by the instruction decoding device 12, and control information relating to instruction execution and control information for operand address calculation and pre-reading are issued to the address calculation device 13. At clock t3, the address calculation unit 13 calculates the operand address in accordance with the control information for operand address calculation and prefetching, and sends the operand address, control information associated with memory reference, and control information relating to instruction execution to the operand prefetching unit 14. To do. At clocks t4 to t6, operand prefetching is performed by operand prefetching device 14 in accordance with the operand address and control information associated with memory reference, and the prefetching data and control information relating to instruction execution are sent to arithmetic device 15. At clock t7, the arithmetic unit 15 executes an operation in accordance with the control unit relating to instruction execution. For instruction 2, the instruction code is prefetched by the instruction prefetching unit 11 at clock t2, and the instruction is decoded by the instruction decoding unit 12 at clock t3. Therefore, only the control information relating to the instruction execution is issued to the address calculation device 13 because the instruction does not require fetching the memory operand. The clock t4 passes through the stage of the address calculation device 13, but does not perform any operation because there is no control information for calculating the address of the operand and prefetching, and attempts to send control information relating to instruction execution to the operand prefetch device 14. However, since the execution of the instruction 1 in the operand prefetching device 14 is not completed, the transmission of the control information of the instruction 2 related to the instruction execution is delayed until the clock t7. Clock t7
Although it passes through the stage of the operand prefetch unit t4, nothing is done because there is no control information for operand address calculation and prefetch, and control information relating to instruction execution is sent to the arithmetic unit 15. At clock t8, the arithmetic unit 15 executes an arithmetic operation in accordance with control information regarding instruction execution.

However, in the above-described configuration, an instruction such as an inter-register operation that does not require fetching of a memory operand also requires unnecessary passage through a pipeline stage such as operand address calculation and prefetching. When the pipeline is disturbed, overhead for filling the pipeline is generated. Further, there is a problem that the bus band for operand access of an instruction originally requiring an operand fetch is limited by unnecessary passage of a pipeline stage of an instruction not requiring a memory operand fetch.

Therefore, in order to solve the above problems, for example, the following patent (Japanese Patent Laid-Open No. 63-167935) has been applied.

FIG. 12 shows a configuration diagram of the data processing device. In FIG. 12, 18 is an instruction pre-reading device for pre-reading an instruction code, 19 is an instruction decoding device, 20 is an address calculation device for performing operand address calculation, 21 is an operand pre-reading device for performing operand pre-reading, and 22 is arithmetic control. Device, 23 is an arithmetic device, 24 is an input / output bus for connecting memory / I / O, etc., 25 is an instruction prefetch device 18, an operand prefetch device 21, and arbitrates input / output requests from the arithmetic device 23 when writing operands. A bus control device for controlling the bus 24.

The instruction decoding device 19 decodes the instruction code prefetched by the instruction prefetching device 18, and when it involves the fetch of the memory operand, the control information for the address calculation and prefetch of the operand, and when it involves the writing to the memory. Control information for calculating the address of the operand is issued to the address calculation device 20. Further, control information regarding instruction execution is issued to the arithmetic and control unit 22.

The address calculation device 20 calculates the address of the operand, and sends the operand address and control information accompanying the memory reference to the operand prefetch device 21.

Operand prefetching device 21 issues a request to bus control device 25 when fetching of a memory operand is necessary, performs memory prefetching according to the operand address received from address calculation device 20, and queues the read data. If it is necessary to write to the memory, the operand address is queued. The state of queuing of the pre-read data and the write address is notified to the arithmetic and control unit 22.

The arithmetic control unit 22 performs queuing of the control information of the arithmetic unit 23 received from the instruction decoding unit 19. In addition, control information is issued in accordance with a request from the arithmetic unit 23. At this time, if the control information to be issued requires prefetch data or a write address, the queuing state of the prefetch data and the write address of the operand prefetch device 21 is confirmed. If not ready, the arithmetic unit
Issuance of control information to 23 is delayed until the preparation of the pre-read data or write address is completed.

The arithmetic unit 23 executes an arithmetic operation according to the control information received from the arithmetic control unit 22 and the prefetch data received from the operand prefetch unit 21. If the operation result needs to be written to the memory, a request is issued to the bus control device 25, and the operation result is written to the memory according to the write address received from the operand prefetch device 21.

The operation of the second conventional data processing device configured as described above will be described below.

FIG. 13 shows an operation timing chart. Instructions executed in the instruction prefetching device 18, the instruction decoding device 19, the address calculation device 20, the operand prefetching device 21, and the arithmetic device 23 are shown in clock units. Here, the instruction prefetch device 18 has a cache memory therein, and the number of clocks required for each device is determined by the instruction prefetch device 18 (1 clock), the instruction decoding device 19 (1 clock), the address calculation device 20 (1 clock), The figure shows the case of the operand prefetch device 21 (3 clocks) and the arithmetic unit 23 (1 clock). The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. 11, and an instruction that does not require fetching two memory operands is executed after an instruction that requires fetching memory operands. ,
These three instructions are repeated. Specifically, the instruction
Instructions 1, 4 are instructions that require fetching memory operands, and instructions 2, 3, 5, 6 are instructions that do not require fetching memory operands. The initial state of the pipeline is empty (for example, at the time of conditional branch). Instruction 1 is the clock
At t1, the instruction prefetching device 18 prefetches the instruction code and issues the instruction code to the instruction decoding device 19. clock
At t2, instruction decoding is performed by the instruction decoding device 19, control information for calculating the address of the operand and prefetching is issued to the address calculation device 20, and control information relating to instruction execution is issued to the operation control device 22. However, since the data preparation is not completed, the issuance of the control information relating to the instruction execution to the arithmetic unit 23 is delayed while the control information is queued in the arithmetic control unit 22. In accordance with control information for operand address calculation and prefetching, the address calculation of the operand is performed by the address calculation device 20 at the clock t3, and the operand prefetching is performed by the operand prefetching device 21 at the clocks t4 to t6. When the preparation of the data is completed, the control information about the instruction execution queued in the arithmetic control unit 22 is issued, and the arithmetic unit 23 is clocked at the clock t7.
Executed in For the instruction 2, the instruction prefetching device 18 prefetches the instruction code at the clock t2, and the clock t3
Then, the instruction decoding unit 19 decodes the instruction and issues only the control information related to the instruction execution to the arithmetic and control unit 22 because the instruction does not need to fetch the memory operand. However, since the issuance of the control information for the instruction 1 is not completed, the control information of the instruction 2 relating to the execution of the instruction is queued in the arithmetic and control unit 22 and issuance to the arithmetic unit 23
Delayed until t8.

According to the second conventional example described above, in an instruction such as an inter-register operation that does not require fetching of a memory operand, unnecessary passage of a pipeline stage such as address calculation of an operand or prefetching is unnecessary. Even if a pipeline disorder such as branching occurs, the overhead for filling the pipeline does not occur.
In addition, the limitation on the bus band for operand access of an instruction that originally requires fetching of an operand, which is caused by unnecessary ventilation of a pipeline stage of an instruction that does not require fetching of a memory operand, is also eliminated.

However, in the configuration described above, when an instruction requiring operand fetch is followed by an instruction requiring writing to the memory, the operation stage of the latter instruction is performed even if the operation requires the former. Without using the execution result of this instruction, it is necessary to wait until the operand prefetch stage and the operation stage of the former instruction are completed. Furthermore, when an instruction that does not require operand fetching or writing to memory follows, the operation stage of the instruction is performed without using the execution result of the instruction that requires operand fetching. One has to wait until the pre-read stage and the operation stage and the operation stage of the instruction that requires writing to the preceding memory are completed. Also, when an instruction that requires writing to memory is followed by an instruction that requires operand fetch, the operation stage of the latter instruction will not be executed even if the execution result of the former instruction is not used for the operation. You must wait until the operand lookahead stage and the operation stage are completed. Furthermore, when an instruction that does not require operand fetching and writing to memory continues, the operation stage of the instruction requires writing to the preceding memory without using the execution result of the instruction requiring operand fetching. One must wait until the operation stage of the instruction, the operand prefetch stage and the operation stage of the instruction requiring the preceding operand fetch are completed. As described above, when an instruction requiring operand fetch and an instruction requiring writing to memory frequently appear in a program successively, the number of execution clocks increases, and the operand fetch such as a subsequent inter-register operation instruction is also written to memory. However, there is a first problem that the execution of an unnecessary instruction is delayed. This problem will be described with reference to the operation timing chart of FIG. The required number of clocks for each device is the same as that shown in FIG. However, the queuing of the write address in the operand prefetching device 21 is one clock, and the arithmetic device
The calculation in 23 and the writing to the memory are performed at 4 clocks. FIG. 14 shows, as a sequence of instructions, an instruction requiring an operand fetch (instruction 1), an instruction for writing a register to memory (instruction 2), and an instruction requiring neither operand fetch nor writing to memory (instruction 3). In the case of instruction 1, the address is calculated at clock t3, the operand is fetched at clocks t4 to t6, and the operation is performed at clock t7. However, the instruction 2 must wait for the completion of the operation stage of the instruction 1 after the address is calculated at the clock t4, and the operation and the writing to the memory are performed at the clocks t8 to t11. The operation of the instruction 3 is delayed until the clock t12.

In view of this point, the present invention can execute both instructions in parallel even if an instruction that requires operand fetch and an instruction that needs to write to memory are consecutive, and operand fetches such as subsequent inter-register arithmetic instructions can also be performed to memory. It is an object of the present invention to provide a data processing device in which execution of an instruction that does not require writing of data is not delayed.

Further, in the conventional configuration, once an instruction that requires an operand fetch is executed once, even if the instruction is an instruction that does not require an operand fetch, the operation stages of subsequent instructions
The instruction look-ahead stage is moved away from time. Therefore, the operation stage becomes vacant, and the number of execution clocks of the instruction that requires the operand fetch that first appears from the pipeline in the empty state is not one clock, and the address calculation device 20, the operand prefetch device 21, and the operation device. The second problem was that it would be the sum of 23 required clocks.
Furthermore, when a conditional branch instruction follows, the instruction prefetch stage of the branch destination instruction is delayed, so that the pipeline interlock time is lengthened, and the third problem is that pipeline efficiency is greatly reduced. Second task
The third problem will be described with reference to the operation timing chart of FIG. 15 and the operation timing chart of FIG. In both figures, the required number of clocks for each device is the same as that shown in FIG. FIG. 15 shows a sequence of instructions, two instructions that do not require operand fetch (instruction 1 and instruction 2), one instruction that requires operand fetch (instruction 3), and two instructions that do not require operand fetch. (Instruction 4, Instruction 5) is shown. Instruction 1 and instruction 2 are calculated at clock t3 and clock t4, respectively, while instruction 3 is calculated at clock t9 because of the address calculation stage and operand prefetch stage. Therefore, during the period of clocks t5 to t8, a vacancy occurs in the operation stage, the number of execution clocks of the instruction 3 requiring operand fetch that first appears from the pipeline in the empty state is 5 clocks, and the operation of the instruction 4 and the instruction 5 is performed. The stage is 6 clocks away from the instruction look-ahead stage. Figure 16 shows one instruction (instruction 1) that requires operand fetch as an instruction sequence.
And a conditional branch instruction (instruction 6) follow four instructions (instruction 2 to instruction 5) that do not require operand fetch, and a branch is taken at the conditional branch instruction 6 to become an instruction (instruction n) that does not require operand fetch. This shows a case where a branch occurs. Instruction 1
Requires an address calculation stage and an operand prefetch stage, the subsequent operation stages of instructions 2 to 6 are separated from the instruction prefetch stage by 6 clocks. Accordingly, the instruction prefetch stage of the branch destination instruction n is clock t13, and in the instruction prefetch stage, an interlock of six clocks from clocks t7 to t12 occurs in the pipeline. Thus, in the conventional configuration,
The appearance of conditional branch instructions with a frequency of as much as 20% in a program causes a significant decrease in pipeline efficiency.

In view of the foregoing, the present invention provides an instruction that requires no operand fetch, followed by an instruction requiring an operand fetch. When the number of execution clocks is one, and when a conditional branch instruction follows, the pipeline interlock time is equal to the case where there is no instruction requiring operand fetch, and the data that minimizes the decrease in pipeline efficiency is obtained. It is an object to provide a processing device.

Further, in the conventional configuration, when a register that is rewritten by an operation of an instruction that does not require operand fetch is read by the address calculation of a subsequent instruction that requires operand fetch, the address calculation stage is an operation stage of an instruction that does not require operand fetch. Interlock until this is completed (this is called address calculation interference), which has a fourth problem that the efficiency of the pipeline is reduced. This problem will be described with reference to the operation timing chart of FIG. The number of clocks required for each device is the same as that shown in FIG. FIG. 17 shows, as an instruction sequence, an instruction requiring an operand fetch (instruction 1), two instructions requiring no operand fetch (instruction 2, instruction 3), and an instruction requiring an operand fetch (instruction 4). And the result of the operation of the instruction 3 is used in the address calculation of the instruction 4. The address calculation of the instruction 4 can be performed at the clock t6 if there is no address calculation interference. However, the calculation is delayed until the next clock t10 when the operation of the instruction 3 for the interference is completed. As described above, in the address calculation stage, the pipeline is interlocked with four clocks t6 to t9, and the address calculation interference causes the pipeline efficiency to be lowered.

In view of the foregoing, the present invention does not generate an interlock even when a register that is rewritten by an operation of an instruction that does not require operand fetch is read by the address calculation of an instruction that requires an operand fetch. It is an object of the present invention to provide a data processing device that does not reduce the power consumption.

Further, in the conventional configuration, when an instruction requiring a plurality of operand fetches or a case involving writing of a plurality of operands to the memory is executed, even if the subsequent instruction does not require the operand fetch, Even if the execution result of an instruction that requires operand fetch or an instruction that involves writing a plurality of operands to memory is not required, the operation of the instruction is performed by an instruction that requires a plurality of operand fetches or a plurality of operands. There is a fifth problem that it is necessary to wait for a long time until an instruction involving writing of an operand to a memory is completed, and the efficiency of the pipeline is reduced. Further, in the conventional configuration, an instruction that requires a plurality of operand fetches or an instruction that involves writing a plurality of operands to the memory is followed by an instruction that requires a plurality of operand fetches or a plurality of operands to the memory. There is a sixth problem in that the performance of software that optimizes a program so that the execution result of an instruction involving writing is not required cannot be exhibited. The fifth and sixth problems will be described with reference to the operation timing chart of FIG. The required number of clocks for each device is the same as that shown in FIG. FIG. 18 shows an instruction sequence in which three operand fetch instructions (instruction 1) are followed by two instructions that do not require operand fetch (instruction 2 and instruction 3).
Instruction 3 shows the case where the execution result of instruction 1 is not required. Instruction 1 prefetches the first operand at clocks t4 to t6, stores the operand in register R1 at clock t7, prefetches the second operand at clocks t7 to t9, and stores the operand in register R2 at clock t10. Then, the third operand is prefetched at clocks t10 to t12, and the operand is stored in the register R3 at clock t13. The operation of the instruction 2 is such that the arithmetic unit 23 is not used at the clock t4 and the instruction 2 is the instruction 1
Although the registers R1, R2, and R3 that are the execution results of the instruction 1 are not used, the clock t1 next to the third operation stage of the instruction 1
Wait until 4 The operation of the instruction 3 is performed by the arithmetic unit 23
Is not used at clock t5, and instruction 3 becomes instruction 1
Even though the registers R1, R2, and R3, which are the execution results of, are not used, the clock t15 is kept waiting. As described above, a long idle time occurs in the arithmetic unit 23, and the efficiency of the pipeline is significantly reduced.

In view of the foregoing, the present invention has been made in consideration of the above circumstances. Even if an instruction requiring a plurality of operand fetches or an instruction involving writing of a plurality of operands to a memory is executed, the subsequent instruction does not require the operand fetch, and If the execution result of an instruction that requires an operand fetch or an instruction that involves writing a plurality of operands to memory is not required, the operation of the instruction is performed using an instruction that requires a plurality of operand fetches or a plurality of operands. An object of the present invention is to provide a data processing device which does not reduce the efficiency of the pipeline by performing the operation in parallel or in advance with the operation of the instruction involving writing the operand to the memory. Further, according to the present invention, an instruction that requires a plurality of operand fetches or an instruction that involves writing a plurality of operands to a memory is an instruction that requires a plurality of operand fetches or a plurality of operands to be written to a memory. It is an object of the present invention to provide a data processing device that exhibits the performance of software that optimizes a program so that the execution result of an accompanying instruction is not required.

All of the above issues are operand prefetch devices.
It becomes remarkable as the required number of clocks of 21 increases. Therefore, in the conventional configuration, the operand read-ahead device 21 is provided with a cache memory for data, and the number of clocks required at the time of a cache hit of the operand read-ahead device 21 is reduced to reduce the first to sixth problems. It is possible to However, as the capacity of the built-in cache memory increases, the hit rate improves, but the access time of the cache memory increases,
There is a new seventh problem that it is difficult to reduce the required number of clocks at the time of a cache hit of the operand prefetch device 21.

In view of the above points, the present invention has the following features, regardless of whether the number of clocks required for reading or writing an operand is increased or decreased depending on whether or not the cache memory is built in, the hit rate of the cache memory, and the capacity of the cache memory. It is an object of the present invention to provide a data processing apparatus which can solve the problem and can set the number of clocks required for reading and writing of an operand independently of the number of execution clocks of an inter-register operation.

Further, in the conventional configuration, in order to reduce the waiting time of the pre-read data in the arithmetic and control unit 22, the instruction decoding unit 19 transmits the address calculation unit 20 as soon as possible before sending the control information relating to the instruction execution to the arithmetic and control unit 22.
It is necessary to send control information for address calculation and look-ahead. Therefore, the control of the instruction decoding device 19 becomes complicated. Further, in the above configuration, complicated control for waiting for the pre-read data or the write address in the arithmetic and control unit 22 is required. As described above, as the control of each device becomes complicated, the delay time of the control circuit increases, and there is an eighth problem that it is not easy to increase the clock frequency at which the processor operates.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a data processing device capable of easily improving the clock frequency at which a processor operates.

Further, the present invention provides a data processing device capable of updating a flag even when a preceding instruction and a succeeding instruction, which are originally sequentially executed, are executed in parallel without any contradiction. The purpose is to provide.

Further, the present invention provides a data processing device capable of updating a flag even when a preceding example which is originally completed in a normal order and a connection instruction are completed in a reverse order, without any inconsistency with a case where the flag is completed in a normal order. The purpose is to

Means for Solving the Problems The invention according to claim 1 comprises at least a read stage, a decoding stage and an execution stage, and the execution stage further includes a serial execution first stage and a second execution stage. In a line-type data processing device, an instruction prefetching unit acting as a reading stage, an instruction decoding unit acting as a decoding stage, at least a first instruction executing unit acting as a first execution stage, and a second execution unit And a second instruction execution means acting as a stage, wherein the first instruction is an instruction that is processed in this order at least in the first instruction execution means and the second instruction execution means. A second instruction following the first instruction is processed in at least the first instruction executing means, and When the instruction does not require processing by the second instruction executing means, the instruction executing means may execute the first instruction even if the second instruction executing means is executing the processing relating to the first instruction. The data processing apparatus is characterized in that the instruction execution means performs the processing related to the second instruction, and completes all the processing of the second instruction in the processing.

According to a second aspect of the present invention, an instruction pre-reading means for pre-reading an instruction, an instruction decoding means for decoding the instruction read by the instruction pre-reading means, and an execution of the instruction according to the decoding result of the instruction decoding means. An instruction executing means for performing processing; a flag generating means for generating a flag indicating a state of an execution result of the instruction executing means; and a status register,
The instruction execution means performs a process related to a first command and a process related to a second command subsequent to the first command in parallel,
The flag generating means, when the processing related to the first instruction and the processing related to the second instruction are executed in parallel in the instruction executing means, among the flags included in the status register, A first flag that is updated by the execution of the first instruction and is not updated by the execution of the second instruction is distinguished from a second flag that is updated by the execution of the second instruction. Generating the first flag based on the execution result of the second instruction, generating the second flag based on the execution result of the second instruction, and reflecting the second flag in the status register. A data processing device.

According to a third aspect of the present invention, an instruction pre-reading means for pre-reading an instruction, an instruction decoding means for decoding the instruction read by the instruction pre-reading means, and an execution of the instruction according to the decoding result of the instruction decoding means. Instruction execution means for performing processing;
A flag generation unit for generating a flag indicating a state of an execution result of the instruction execution unit; and a status register, wherein the instruction execution unit performs processing related to a first instruction and a second instruction subsequent to the first instruction. The processing related to the instruction is completed in an order irrelevant to the order of the program, and the flag generating means completes the processing related to the first instruction after the processing related to the second instruction is completed in the instruction executing means. In this case, the data processing device is configured to generate a flag updated by the execution of the first instruction and not updated by the execution of the second instruction and reflecting the flag in the status register. .

The invention according to claim 1 has the configuration described above, and all processing related to the second instruction is performed in the first instruction execution means without having the completion of the processing related to the first instruction in the second instruction execution means. To complete. According to the second aspect of the present invention, when the first flag that is updated by the execution of the preceding first instruction and is not updated by the execution of the subsequent second instruction is identified, the first flag is set. Generated based on the execution result of the first instruction, reflected in the status register, and updated by the execution of the subsequent second instruction whether or not updated by the execution of the preceding first instruction. If the second flag is identified, a second flag is generated based on the execution result of the second instruction and reflected in the status register.

According to the third aspect of the present invention, with the configuration described above, at the time when the process related to the second instruction is completed, a flag updated by execution of the second instruction is generated and reflected in the status register, After that, when the processing related to the first instruction is completed, a flag that is updated by the execution of the first instruction, and is not updated by the execution of the second instruction, is generated in the status register. reflect.

Embodiment FIG. 1 shows a configuration diagram of a data processing apparatus according to an embodiment of the present invention. In FIG. 1, 1 is an instruction prefetching device for prefetching an instruction code, 2 is an instruction decoding device, 3 is a first arithmetic device, 4 is an operand reading device for reading operands, 5 is a second arithmetic device, and 6 is Operand writing device for writing operands to memory, 7 an input / output bus for connecting memories and I / Os, 8 arbitrating requests from instruction prefetch device 1 and operand reading device 4 and controlling input / output bus 7 The bus control device performs the following.

The instruction decoding device 2 decodes the instruction code pre-read by the instruction pre-reading device 1 to obtain control information related to instruction execution,
Control information for calculating and reading the address of the operand when fetching the memory operand and control information for calculating and writing the address of the operand when writing to the memory are issued to the first arithmetic unit 3.

When the instruction is an inter-register operation or a register / immediate operation, the first operation device 3 executes the operation in accordance with the control information received from the instruction decoding device 2. When an instruction involves fetching a memory operand, the address of the operand is calculated in accordance with the control information received from the instruction decoding device 2, and the operand address, control information associated with memory reference, and control information relating to instruction execution are sent to the operand reading device 4. . When the instruction involves writing to the memory, the write address is calculated in accordance with the control information received from the instruction decoding device 21, and the write address and the control information accompanying the memory writing are sent to the operand writing device 6.

Operand reading device 4 issues a request to bus control device 8 and reads the memory according to the operand address received from first arithmetic unit 3. The read data is sent to the second arithmetic unit 5 together with the control information regarding the instruction execution.

The second arithmetic unit 5 executes the arithmetic according to the data received from the operand reading unit 4 and the control information regarding the instruction execution. The calculation result is returned to the first calculation device 3.

The operand writing device 6 fetches write data from the first arithmetic device 3, issues a request to the bus control device 8 through the operand read device 4, and performs writing to the memory according to the write address received from the first arithmetic device 3.

FIG. 2 is a detailed block diagram of the first arithmetic unit 3, the operand reading unit 4, the second arithmetic unit 5 and the operand writing unit 6 shown in FIG. In FIG.
301, an arithmetic control circuit for controlling the first arithmetic unit 3 in accordance with control information relating to instruction execution and control information for calculating an address of an operand received from the instruction decoding unit 2;
302 is a general-purpose register, 303 is a register control circuit that controls the general-purpose register 302, 304 is a first arithmetic logic operation circuit that calculates data stored in the general-purpose register 302, 305 is a stator register, and 306 is a stator register 305. A flag generation circuit for generating flag information of a calculation result, which is implemented in the first calculation device 3. 401 is a read address register for holding an address for reading the memory, 40
2 receives from the arithmetic and control circuit 301 control information accompanying the memory read, including information (register list) specifying a register for storing a result of reading a plurality of operands, and controls the operand read device 4 and the register control circuit 303. A read control circuit 403; a read data buffer 403 for holding read data received from the bus control device 8;
Reference numeral 404 denotes a read address increment circuit for increasing the content of the read address register 401 by a constant value. 501 is the read data buffer 403
And a second arithmetic and logic circuit that performs an operation on the data stored in the general-purpose register 302 and is implemented in the second arithmetic unit 5. 601 is a write address register for holding an address for writing to the memory, and 602 is arithmetically controlled for control information associated with writing to the memory, including information (register list) for specifying a register storing operands when writing a plurality of operands. A write control circuit which receives from the circuit 301 and controls the operand writing device 6 and the register control circuit 303; 603, write data which is taken in from the general-purpose register 302 or write data which holds the write data received from the second arithmetic logic operation circuit 501 A buffer, 604, is a write address increment circuit that increments the contents of the write address register 601 by a fixed value, and the above is implemented in the operand writing device 6. The flag generation circuit 306 receives information about flag generation from the first arithmetic logic operation circuit 304 and the second arithmetic logic operation circuit 501, and generates a flag.

The operation of the data processing apparatus of this embodiment configured as described above will be described below.

FIG. 3 shows the relationship between the instruction type and the flow of the pipeline stage. Here, IF is the instruction prefetch stage in the instruction predecessor device 1, and DEC is the instruction decoding device 2.
, EX1 is the first operation stage in the first operation device 3, OF is the operand operation stage in the operand operation device 4, EX2 is the second operation stage in the second operation device 5, and OS is the operand in the operand operation device 6. Represents a writing stage. The instruction is prefetched by the instruction prefetching device 1 and decoded by the instruction decoding device 2. The subsequent processing flow differs depending on the type of instruction.

(A) is a case of a register-to-register operation instruction or a register-immediate-value operation instruction. The process ends with the calculation in the first calculation device 3. That is, the first arithmetic unit 3 includes the general-purpose register 302
Is calculated by the first arithmetic and logic operation circuit 304 and stored in the general-purpose register 302.

(B) is a case of an instruction for performing a memory-register operation and storing the result in the register. It also includes instructions that do not involve computation (load). The processing ends with the flow of the operand address calculation in the first arithmetic unit 3, the operand reading in the operand read unit 4, and the arithmetic in the second arithmetic unit 5. That is, the first arithmetic unit 3 includes a first arithmetic and logic operation circuit
The read address of the operand is calculated at 304 and sent to the read address register 401. Operand reading device 4
Passes the read address held in the read address register 401 to the bus control device 8 and once reads the read data received from the bus control device 8 from the read data buffer 403.
To hold. The second arithmetic unit 5 includes a read data buffer
The read data held in 403 is operated by the second arithmetic and logic operation circuit 501 together with the contents of the general register 302 as one operand, and the result is stored in the general register 302. When the instruction does not involve an operation, the second arithmetic and logic operation circuit 501 functions to pass the contents of the read data buffer 403 as it is.

(C) writes the contents of the register to the memory (store)
This is the case for instructions. The processing ends with the calculation of the write address in the first arithmetic unit 3 and the writing to the memory in the operand writing unit 6. That is, the first arithmetic unit 3
The arithmetic logic operation circuit 304 calculates the write address of the operand and sends it to the write address register 601. The operand writing device 6 takes in the write data from the general-purpose register 302, temporarily holds it in the write data buffer 603, and then sends it to the bus controller 8 together with the write address held in the write address register 601 to write it in the memory.

(D) is a case of an instruction for performing an operation between the register and the memory and writing the result to the memory. The memory operand in this case is read → update → write. The processing ends with the calculation of the address of the operand in the first arithmetic unit 3, the reading of the operand in the operand reading unit 4, the calculation in the second arithmetic unit 5, and the writing of the calculation result in the operand writing unit 6 into the memory. . That is, the first arithmetic unit 3
The arithmetic / logic operation circuit 304 calculates the read / write address of the operand and sends it to the read address register 401 and the write address register 601. Operand reading device 4
Passes the read address held in the read address register 401 to the bus control device 8 and once reads the read data received from the bus control device 8 from the read data buffer 403.
To hold. The second arithmetic unit 5 includes a read data buffer
The read data held in 403 is operated by the second arithmetic and logic operation circuit 501 together with the contents of the general-purpose register 302 as one operand, and the result is stored in the write data buffer 603. The operand writing device 6 sends both the write address held in the write address register 601 and the write data held in the write data buffer 603 to the bus control device 8, and writes the data to the memory.

(E) is a case of an instruction for performing an operation between a plurality of memory operands having consecutive addresses and a register and storing a plurality of results in a plurality of registers. Instructions without operations (multiple loads) are also included. The processing is performed by the first arithmetic unit 3
After the calculation of the address of the first memory operand in 1), the reading of the operand in the operand reading device 4 and the calculation in the second arithmetic device 5 are repeated. However, the reading of the next operand by the operand reading device 4 and the operation by the second arithmetic device 5 are executed in parallel. That is, the first arithmetic unit 3 calculates the read address of the first operand in the first arithmetic and logic operation circuit 304, and
And a register list indicating a register group for storing the result is read from the arithmetic control circuit 301 and sent to the read control circuit 402. At this time, the register control circuit 303 prohibits reading of the register group that stores the result of the general-purpose register 302. The operand reading device 4 transfers the read address held in the read address register 401 to the bus control device 8, and at the same time, increases the fixed value by the read address increment circuit 404 and holds the read address in the read address register 401 again. The read data received from the bus controller 8 is once held in the read data buffer 403. The second arithmetic unit 5 performs an arithmetic operation on the read data held in the read data buffer 403 together with the contents of the general-purpose register 302 which is one of the operands, and stores the result in the general-purpose register 302. When the instruction does not involve an operation, the second arithmetic and logic operation circuit 501 functions to pass the contents of the read data buffer 403 as it is. At the same time, the read control circuit 402 notifies the register control circuit 303 that one of the results is stored in the general-purpose register 302, and the register control circuit 303 receives this and prohibits the general-purpose register 302 from reading the register. To release. For the second and subsequent operands, the operand reading device 4 and the second arithmetic device 5 are independent of the first arithmetic device 3 and perform incremental addition of operand addresses, reading of memory operands, calculation, storage of results, reading of the register. Is repeatedly released. At this time, the operand reading device 4 and the second arithmetic device 5 form a pipeline and execute them in parallel.

(F) is a case of an instruction to write the contents of a plurality of registers into a memory having consecutive addresses (multiple store). After the write address of the first register is calculated by the first arithmetic unit 3, the process is repeated by repeating the writing to the memory by the operand write unit 6. That is, the first arithmetic unit 3
Calculates the write address of the first operand in the first arithmetic logic operation circuit 304, sends it to the write address register 601, and sends a register list showing a register group to be written in the memory from the operation control circuit 301 to the write control circuit 602. . At this time, the register control circuit 303 sets the general-purpose register 3
Inhibits writing to the registers that are written to the 02 memory. The operand writing device 6 fetches the write data from the general-purpose register 302 according to the write control circuit 602, temporarily holds it in the write data buffer 603, and then sends it to the bus controller 8 together with the write address held in the write address register 601 to the memory. At the same time that the write address is written, the write address increment circuit 604 increments it by a constant value and holds it again in the write address register 601. At the same time, the write control circuit 602 notifies the register control circuit 303 that one of the registers has been held in the write data buffer 603.
Release the prohibition of writing to the corresponding register of 02. Regarding the second and subsequent operands, the operand writing device 6 repeats the reading of the register, the incremental addition of the operand address, the writing to the memory, and the release of the prohibition of the writing of the register, independently of the first arithmetic unit 3. .

As described above, in the data processing apparatus according to the present embodiment, the first arithmetic unit 3 separates the subsequent processing, and the operand reading unit 4 and the second arithmetic unit 5 or the operand writing unit 6
Is an instruction prefetching device 1, an instruction decoding device 2, a first arithmetic device 3
Independently executes the subsequent processing of the instruction.

FIG. 4 shows an operation timing chart. The instruction executed in the instruction prefetching device 1, the instruction decoding device 2, the first arithmetic device 3, the operand reading device 4, and the second arithmetic device 5 and the change of the contents of the status register 305 are shown in clock units. Where the instruction prefetcher
Reference numeral 18 has a cache memory therein, and the number of clocks required for each device is the instruction prefetching device 1 (1 clock), the instruction decoding device 2 (1 clock), the first arithmetic unit 3 (1 clock), and the operand reading device 4 ( 3 clocks) and the second arithmetic unit 5 (1 clock). The instruction sequence that is being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. 13, and two instruction operations between registers are executed following the instruction for storing the operation register between the memory and the register. It has become a repetition. Specifically, instructions 1 and 4 are memory / register arithmetic operation register storage instructions, and instructions 2, 3, 5, and 6 are inter-register arithmetic operation instructions. The initial state of the pipeline is empty (for example, at the time of conditional branch). Instruction 1 is prefetched by the instruction prefetching device 1 at a clock t1 and issues the instruction code to the instruction decoding device 2. At the clock t2, the instruction decoding device 2 decodes the instruction, and issues to the first arithmetic unit 3 control information for calculating and reading the address of the operand and control information for executing the instruction. In accordance with control information for operand address calculation and reading, operand address calculation is performed by first arithmetic unit 3 at clock t3, and operand reading is performed by operand reading device 4 at clocks t4 to t6. The read data and the control information relating to the instruction execution are sent to the second arithmetic unit 5, and are calculated by the second arithmetic unit 5 at the clock t7. For the instruction 2, the instruction code is prefetched by the instruction prefetching device 1 at the clock t2, the instruction is decoded by the instruction decoding device 2 at the clock t3, and only the control information relating to the instruction execution is issued to the first arithmetic unit 3. The calculation is performed by the first calculation device 3 at the clock t4. Similarly, the instruction 3 is the first arithmetic unit 3 at the clock t5.
Is calculated by

In this way, the instruction 2 and the instruction 3 are operated in advance of the instruction 1, and the instruction 5 is operated in parallel with the instruction 1. The flag generation circuit 306 receives the first arithmetic logic operation circuit 304 at the clock t4.
Generates a flag for instruction 2 based on the information obtained from
Reflected in the status register 305 at the clock t5. At this time, the updated flag is stored. Also, clock t5
Then, the flag of the instruction 3 is generated based on the information obtained from the first arithmetic logic operation circuit 304, and the flag is reflected in the status register 305 at the clock t6. At this time also, the updated flag is stored. Next, the flag generation circuit 306 outputs the clock t
7, the flag of the instruction 5 is set based on the information obtained from the first arithmetic logic operation circuit 304, and the second arithmetic logic operation circuit 501
The flag of the instruction 1 is generated based on the information obtained from. However, at this time, of the flags updated by instruction 1,
No new flag is generated for the same flag updated at clocks t5 and t6. Further, if there is the same flag updated by the instruction 1 as the flag updated by the instruction 5, the instruction 5 is preferentially generated even if it is the same as the flag updated by the clocks t5 and t6. . The generated flag is reflected in the status register 305 at clock t8.

As described above, according to the present embodiment, the order in which the instructions are operated does not always match the order in which the programs are executed. However, the flag can be reflected in the status register 305 by performing arbitration of the flag generated by the flag generation circuit 306 without any contradiction with the case where the instructions are operated in the program order.

FIG. 5 is an operation timing chart for explaining that the present embodiment solves the first problem. The number of clocks required for each device is the same as that shown in FIG. However, the number of clocks required for writing to the memory in the operand writing device 6 is three. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. A case is shown in which a memory / register operation register storage instruction (instruction 1), a register transfer (store) instruction (instruction 2), and an inter-register operation instruction (instruction 3) follow. Instruction 1 is a clock
The address is calculated at t3, the operand is fetched at clocks t4 to t6, and the operation is performed at clock t7. However, after the address of the instruction 2 is calculated by the first arithmetic unit 3 at the clock t4, the subsequent processing is separated, and the transfer of the register to the memory is performed by the operand writing unit 6 independently of the first arithmetic unit 3. . That is, the operand writer 6 is clocked
At t5, write data is fetched from the general-purpose register 302 to the write data buffer 603, and at clocks t7 to t9, the write address held in the write address register 601 and the write data held in the write data buffer 603 are sent to the bus controller 8. Write to memory. The instruction 3 is operated at the clock t5 in parallel with the memory read of the instruction 1 and the memory write of the instruction 2.

As described above, according to the present embodiment, an instruction that requires an operand fetch and an instruction that does not require a subsequent operand fetch or writing to a memory, an instruction that requires a memory writing and a subsequent operand fetch are also stored in a memory Instructions that do not require writing, instructions that require operand fetching and instructions that require writing to subsequent memory, instructions that require writing to memory, and instructions that require subsequent operand fetching are executed in parallel. It can be executed, and the execution time of the instruction sequence can be shortened.

FIG. 6 is an operation timing chart for explaining that the present embodiment solves the second problem. The required number of clocks for each device is the same as that shown in FIG. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. 15, and two memory operation instructions (instruction 1, instruction 2) are followed by one memory instruction.
Inter-register operation register storage instruction (instruction 3), and 2 more
The case where one inter-register operation instruction (instruction 4, instruction 5) continues is shown. Instruction 3 performs address calculation at clock t5, and operands are read from the memory at clocks t6 to t8, and are operated at clock t9. However, since the operand reading device 4 and the second arithmetic device 5 operate independently of the first arithmetic device 3, the instruction 4 and the instruction 5 are sent to the first arithmetic device 3 in parallel with the reading of the memory of the instruction 3 by the clock t6. ,
Operation can be performed at clock t7, and no empty pipeline stage occurs.

As described above, according to the present embodiment, even when an instruction requiring an operand fetch is followed by an instruction requiring an operand fetch, no empty space is generated in the operation stage, and the first operand fetch from the empty pipeline is not executed. The number of execution clocks of a necessary instruction can be one clock.

FIG. 7 is an operation timing chart for explaining that the present embodiment solves the third problem. The required number of clocks for each device is the same as that shown in FIG. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing chart of FIG.
Inter-register operation A register store instruction (instruction 1) and four inter-register operation instructions (instruction 2 to instruction 5) are followed by a conditional branch instruction (instruction 6). In conditional branch instruction 6, a branch is taken and inter-register operation is performed. The figure shows a case of branching to an instruction (instruction n). Although instruction 1 requires operand address calculation and operand reading from memory, the operand reading device 4 and the second arithmetic device 5 operate independently of the first arithmetic device 3, so that the instruction 2 6 is instruction 1
In the first arithmetic unit 3 from the clock t4 to the clock t8 in parallel with the reading of the memory. Therefore, the instruction prefetch stage of the branch destination instruction n is advanced to the clock t9, and in the instruction prefetch stage, the pipeline generates only two in-clocks of the clocks t7 to t8.

As described above, according to the present embodiment, even when an instruction requiring an operand fetch is followed by a conditional branch instruction, the interlock time of the pipeline is made equal to that when no instruction requires the operand fetch, and Efficiency loss can be minimized.

FIG. 8 is an operation timing chart for explaining that the present embodiment solves the fourth problem. The required number of clocks for each device is the same as that shown in FIG. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. 17, and is followed by an instruction for storing an operation register between memory and registers (instruction 1), followed by an operation instruction for two registers (instruction 2). , Instruction 3), and memory
A case is shown in which an inter-register operation register storage instruction (instruction 4) continues and the operation result of instruction 3 is used in the address calculation of instruction 4. Since both the address calculation and the register-to-register calculation are performed by the first arithmetic unit 3, the address calculation of the instruction 4 can be performed at the next clock t6 when the calculation of the instruction 3 is completed, and the pipeline interlock due to the address calculation interference is prevented. Does not occur.

As described above, according to the present embodiment, even when a register to be rewritten by an operation of an instruction that does not require an operand fetch is read by the address calculation of a subsequent instruction that requires an operand fetch, no interlock occurs. It is possible to prevent the efficiency of the pipeline from decreasing.

FIG. 9 is an operation timing chart for explaining that the present embodiment solves the fifth and sixth problems. The required number of clocks for each device is the same as that shown in FIG.
The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. 18, and the instruction (instruction 1) for transferring three memory operands having consecutive addresses to three registers (instruction 1). Followed by two register-to-register operation instructions (instruction 2 and instruction 3), and
Instruction 2 and instruction 3 show the case where the execution result of instruction 1 is not required. Instruction 1 reads the first operand at clocks t4 to t6, stores the operand in register R1 at clock t7, reads the second operand at clocks t7 to t9, and stores the operand in register R2 at clock t10. Then, the third operand is read out at clocks t10 to t12, and the operand is stored in the register R3 at clock t13. However, after the first arithmetic unit 3 calculates the address of the first operand at the clock t3, the operand reading unit 4 and the second arithmetic unit 5
Since it operates independently of the arithmetic unit 3, the following instructions 2 and 3 can be operated in the first arithmetic unit 3 at clocks t4 and t5 in parallel with the reading of the memory of the instruction 1 and the storage of the register. Therefore, there is no long vacant time required for memory reading in the first arithmetic unit 3.

The same applies to the case of a (multiple store) instruction for writing the contents of a plurality of registers into a memory having consecutive addresses. After the first arithmetic unit 3 calculates the address of the first operand, the operand writing unit 6 Since it operates independently of the first arithmetic unit 3, subsequent instructions can be operated in the first arithmetic unit 3 in parallel with the writing of an instruction for writing the contents of a plurality of registers into a memory having continuous addresses. . Therefore, the first arithmetic unit 3 does not have a long free time for writing to the memory.

As described above, according to the present embodiment, even if an instruction that requires a plurality of operand fetches or an instruction that involves writing a plurality of operands to a memory is executed, the subsequent instructions do not require an operand fetch, If the execution result of an instruction that requires a plurality of operand fetches or an instruction that involves writing a plurality of operands to memory is not required, the operation of the instruction is performed using an instruction that requires a plurality of operand fetches. Alternatively, the efficiency of the pipeline can be prevented from being lowered by performing the operation in parallel or in advance with the operation of the instruction that involves writing a plurality of operands to the memory.

Further, according to the present embodiment, an instruction that requires a plurality of operand fetches or an instruction that follows an instruction that involves writing a plurality of operands to a memory is transferred to an instruction that requires a plurality of operand fetches or a plurality of operands of memory. It is possible to exert the performance of software that optimizes a program so that the execution result of an instruction accompanied by writing of is unnecessary.

Next, a description will be given of how the present embodiment solves the seventh problem. In the data processing device of the present embodiment configured as described above, after the first arithmetic unit 3 calculates the address of the operand, the subsequent processing is separated, and the operand reading device 4, the second arithmetic device 5, and the operand writing Device 6 for the first
Since the operation is performed independently of the arithmetic unit 3, subsequent instructions can be operated in the first arithmetic unit 3 in parallel with reading and writing of the memory. As a result, even if the number of clocks required for the operand reading device 4 or the operand writing device 6 is increased, the operation stage of the instruction following the instruction accompanied by the memory reading or writing is not delayed. In addition, even if the required number of clocks of the operand reading device 4 or the operand writing device 6 is reduced by incorporating a cache memory for data, the temporal position of the operation stage of the instruction following the instruction accompanying the memory reading or writing does not change. .

As described above, according to the present embodiment, regardless of whether the built-in cache memory is included, the hit rate of the cache memory, the capacity of the cache memory, and the like, the number of clocks required for reading and writing operands increases and decreases. 6 can be solved, and the number of clocks required for reading and writing of the operand can be set independently of the number of execution clocks of the inter-register operation.

Finally, it will be described that the present embodiment solves the eighth problem. The data processing device according to the present embodiment configured as described above does not prefetch the memory operand. Therefore, the instruction decoding device 2 does not need to issue control information for address calculation prior to control information related to instruction execution, and may issue all control information to the first arithmetic device 3 at the same time. Therefore, the control of the command decoding device 2 is simplified. Also, there is no need for complicated control for waiting for pre-read data or write addresses.

As described above, according to the present embodiment, the delay time of the control circuit is reduced along with the simplification of the control of each device, and the clock frequency at which the processor operates can be easily improved.

In the present embodiment, when executing an instruction to read a single or a plurality of operands from a memory and store them in a register without performing an operation (load or multiple load), the contents of the read data buffer 403 are used as the second arithmetic logic Although it is stored in the general-purpose register 302 through the arithmetic circuit 501, the general-purpose register 3 is directly read from the read data buffer 403.
A data line leading to 02 may be provided and stored in the general-purpose register 302. By doing so, the load instruction and the multiple load instruction that frequently appear in the program do not require the second operation stage, and the pipeline interlock that occurs when the execution result of these instructions is used in the subsequent instructions is eliminated. Therefore, there is an effect that the efficiency of the pipeline is improved. However, when the flag is changed by a load instruction or a multiple load instruction, it is necessary to send information about flag generation from the read data buffer 403 to the flag generation circuit 306.

Although the present embodiment does not consider an address translation mechanism for real storage, an address translation mechanism may be incorporated in the instruction prefetching device 1 and the operand reading device 4 or the bus control device 8 for virtual storage.

Further, in the present embodiment, the operand reading device 4 and the second arithmetic device 5 are separated, but they may be realized as one device as the operand reading device.

Further, in this embodiment, each device is described as one pipeline stage, but may be realized as a device having a plurality of pipeline stages.

Effects of the Invention As described above, according to the first aspect of the present invention,
Even if the processing time of the preceding instruction by the second instruction execution means is long, if the subsequent instruction does not require processing by the second instruction execution means, the subsequent instruction can be processed and completed. In addition, since the first instruction execution means and the second instruction execution means merely form a pipeline connected in series in this order, complicated parallel stage control is not required.

According to the second aspect of the present invention, even when the first instruction and the second instruction, which are originally executed sequentially, are executed in parallel, the flag is set without inconsistency with the case of being executed sequentially. Can be updated.

According to the third aspect of the present invention, even when the first instruction and the second instruction that are originally completed in the normal order are completed in the reverse order, the flag is updated without inconsistency with the case where the first instruction and the second instruction are completed in the normal order. be able to.

As described above, the practical effect of the present invention is extremely large.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing device in an embodiment of the present invention, and FIG. 2 is a detailed configuration diagram of a first arithmetic device 3, an operand reading device 4, a second arithmetic device 5 and an operand writing device 6 of the same embodiment. FIG. 3 is a diagram showing the relationship between the instruction type and the pipeline stage of the embodiment, FIG. 4 is an operation timing diagram of the embodiment, and FIG. 5 is a diagram illustrating the solution of the first problem. FIG. 6 is an operation timing chart of the embodiment explaining that the second problem is solved. FIG. 7 is an operation timing diagram of the embodiment explaining that the third problem is solved. FIG. 8, FIG. 8 is an operation timing chart of the embodiment explaining solving the fourth problem, FIG. 9 is an operation timing diagram of the embodiment explaining solving the fifth and sixth problems, FIG. 10 is a configuration diagram of a first conventional data processing apparatus, 11 figure operation timing diagram of the first conventional example, FIG. 12 is a structural view of a second conventional data processing apparatus, FIG. 13 timing diagram of the second conventional example, 14
FIG. 15 is an operation timing diagram of the second conventional example illustrating the first problem, FIG. 15 is an operation timing diagram of the second conventional example illustrating the second problem, and FIG. 16 is a third problem. FIG. 17 is an operation timing chart of the second conventional example explaining the fourth problem, and FIG. 18 is a diagram explaining the fifth and sixth problems of the second conventional example. FIG. 11 is an operation timing chart of the second conventional example. 1 ... Instruction prefetching device, 2 ... Instruction decoding device, 3 ... First arithmetic device, 4 ... Operand reading device, 5 ... Second
Arithmetic unit 6, operand write unit 7, input / output bus 8, bus control unit 301 arithmetic control circuit 302
...... General purpose register, 303 ...... Register control circuit, 304 ......
1st arithmetic logic operation circuit, 305... Status register, 3
06: flag generation circuit, 401: read address register, 402: read control circuit, 403: read data buffer, 404: read address increment circuit, 501: second arithmetic logic operation circuit, 601: write Address register, 602
... Write control circuit, 603 ... Write data buffer, 6
04 …… Write address increment circuit.

Front page continuation (72) Inventor Takashi Sakao 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-62-262141 (JP, A) JP-A-63-261428 (JP) , A) JP 58-90247 (JP, A) JP 58-106641 (JP, A) JP 57-168350 (JP, A) JP 54-67348 (JP, A) JP 58-189738 (JP, A) JP-A-54-47438 (JP, A)

Claims (3)

(57) [Claims] 1. A pipelined data processing device comprising at least a read stage, a decryption stage and an execution stage, the execution stage further including a serial first execution stage and a second execution stage. Pre-reading means acting as a decoding stage, an instruction decoding means used as a decoding stage, at least a first instruction executing means acting as a first execution stage, and a second instruction executing means acting as a second execution stage An instruction executing means consisting of: a first instruction is a name processed at least in the first instruction executing means and the second instruction executing means in this order, and is a successor to the first instruction. A second instruction to execute is processed in at least the first instruction executing means,
And, when the instruction does not require processing in the second instruction execution means, the instruction execution means, even if the second instruction execution means is executing the processing according to the first instruction, A data processing device, characterized in that the first command execution means performs a process related to the second command and completes all the processes of the second naming. 2. An instruction prefetching means for prefetching an instruction, an instruction decoding means for decoding an instruction read by the instruction prefetching means, and an instruction execution process according to a decoding result of the instruction decoding means. An instruction execution unit; a flag generation unit that generates a flag indicating a state of an execution result of the instruction execution unit; and a status register. The instruction execution unit includes: a process related to a first instruction; The process according to the subsequent second instruction is performed in parallel, and the flag generation unit executes the process according to the first instruction and the process according to the second instruction in parallel in the instruction execution unit. The first flag is updated by execution of the first instruction, and is not updated by execution of the second instruction, among the flags included in the status register; and Identifying a second flag updated by execution of the instruction, generating the first flag based on the execution result of the first instruction, and generating the second flag based on the execution result of the second instruction. The data processing device is characterized in that each of the flags is generated and reflected in the status register. 3. An instruction pre-reading means for pre-reading an instruction, an instruction decoding means for decoding the instruction read by the instruction pre-reading means, and an instruction execution process according to the decoding result of the instruction decoding means. An instruction execution unit; a flag generation unit that generates a flag indicating a state of an execution result of the instruction execution unit; and a status register. The instruction execution unit performs processing related to a first instruction and performs processing on the first instruction. The processing related to the subsequent second instruction is completed in an order irrelevant to the order of the program, and the flag generation unit determines that the processing related to the first instruction corresponds to the second instruction in the instruction execution unit. When completed after the completion of the processing, the status register is generated by generating a flag that is updated by the execution of the first instruction and is not updated by the execution of the second instruction. The data processing apparatus characterized by reflecting.