JPH0296234A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a data processor which can shorten the executing time of an instruction train without deteriorating the pipeline efficiency by providing the 1st and 2nd arithmetic units and the operand reading and writing devices to the stages following an instruction decoder. CONSTITUTION:An arithmetic unit 3 which works independently carries out such an instruction that requires no fetching action of an operand of the inter- register arithmetic, etc., nor writing action to a memory. While an operand reading device 4, transfer means (6 - 8), and an arithmetic unit 5 carry out the instructions requiring the reading actions out of an operand memory. Then an operand writing device 6 and the transfer means (4, 7 and 8) carry out the instructions requiring the writing actions to the operand memory. Thus it is possible to carry out in parallel such continuous instruction trains as the instructions requiring the operand fetching actions and the subsequent instructions requiring no operand fetching action. As a result, the executing time of the instruction trains can be reduced and at the same time the deterioration of the pipeline efficiency can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device aimed at increasing the speed of a computer.

Conventional technology An example of a conventional data processing device is "Computer System Technology" by Tatsu Motooka (April 20, 1972).

Ohmsha, pp. 93-99.

FIG. 10 shows a configuration diagram of this conventional data processing device. In FIG. 10, 11 is an instruction prefetching device for prefetching instruction codes, 12 is an instruction decoding device, and 13
14 is an address calculation device that calculates the address of an operand, 14 is an operand prefetch device that prefetches an operand, 15 is an arithmetic unit, 16 is an input/output bus that connects memory, Ilo, etc., and 17 is an instruction prefetch device 11, an operand prefetch device. 14, and a bus control a1 device that arbitrates requests from the arithmetic unit 16 when writing operands and controls the input/output bus 160.

The instruction decoding device 12 decodes the instruction code prefetched by the instruction prefetching device 11, and sends control information related to instruction execution and, if a memory operand is fetched, operand address calculation and prefetch storage control information to the memory. If writing is involved, control information for calculating the address of the operand is regularly sent to the address calculation device 13.

The AF''!/s calculation device 13 calculates the address of the operand, and sends the operand address, control information associated with memory reference, and control information related to instruction execution to the operand prefetch device 14.

Operand prefetch device 14 issues a request to bus control device 17 when it is necessary to fetch a memory operand, and performs prefetch of the operand according to the operand address received from address calculation device 13. Bus polishing equipment 1
The pre-read data of the operand received from 7, the write address of the operand when writing to memory is involved, and the INI tl information regarding instruction execution received from the address calculation device 13 are sent to the arithmetic device 15.

The arithmetic unit 15 executes arithmetic operations in accordance with the prefetch data and instruction execution control information received from the operand prefetch unit 14 . If it is necessary to write the result of the operation to the memory, a request is sent to the bus control device 17, and the result of the operation is written to the memory according to the write address received from the operand look-ahead device 14.

The operation of the conventional data processing apparatus configured as described above will be described below.

FIG. 11 shows an operation timing chart.

Instructions being executed in the instruction prefetching device 11, instruction decoding device 12, address calculation device 13, operand prefetching device 14, and arithmetic unit 16 are shown in clock units. Here, the instruction prefetching device 11 has an internal cache memory, and the required number of clocks for each device is: instruction prefetching device 11 (1 clock), instruction decoding device 12 (1 clock), address calculation device 13 (1 clock), Operand look-ahead device 14 (3 clocks) and arithmetic device 1
5 (1 clock) is shown. The instruction sequence being executed is an instruction that requires a memory operand fetch, followed by two instructions that do not require a memory operand fetch, and these three instructions are repeated. Specifically, instructions 1 and 4 are instructions that require 7 fetches of memory operands, and instructions 2, 3, 6, and 6 are instructions that do not require fetching of memory operands. The initial state of the pipeline is an empty state (for example, at the time of a conditional branch). For the instruction 1, the instruction code is prefetched by the instruction prefetching device 11 at clock t1, and the instruction code is issued to the instruction decoding device 12. At clock t2, the instruction decoding device 12 decodes the instruction, and issues control information regarding instruction execution and control information for operand address calculation and prefetching to the address calculation device 13. At clock t3, the address calculation device 13 calculates the address of the operand in accordance with the control information a1 for calculating the address of the operand and reading ahead, and reads the operand address, control information associated with memory reference, and control information regarding instruction execution. It is sent to the device 14.

From clock t4 to t6, operand prefetching is performed in operand prefetching device 14 according to the operand address and control information associated with memory reference, and prefetching data and control information regarding instruction execution are sent to arithmetic unit 16. At clock t7, the arithmetic unit 16 executes an arithmetic operation according to control information regarding instruction execution. Instruction 2 is clock t2
At clock t3, the instruction code is prefetched by the instruction prefetch device 11, and the instruction is decoded by the instruction decoder 12 at clock t3.Since the instruction does not require 7 etching of the memory operand, only control information related to instruction execution is sent to the address calculation device 13. Issue to. It passes through the stage of the address calculation device 13 at clock t4, but since there is no control information for operand address calculation and prefetching, nothing is done, and control information regarding instruction execution is sent to the operand prefetching device 14. However, the operand lookahead device 14 of instruction 1
Since execution at t has not been completed, the sending of control information for instruction 2 regarding instruction execution is delayed until clock t7.

It passes through the stage of the operand look-ahead device 14 at clock t7, but since there is no control 1 blueprint for operand address calculation and look-ahead, nothing is done, and control information regarding instruction execution is sent to the arithmetic unit 15. At clock t8, the arithmetic unit 16 executes arithmetic operations in accordance with the antibacterial information regarding instruction execution.

However, in the above configuration, even instructions such as inter-register operations that do not require fetching of memory operands require unnecessary passage through pipeline stages such as operand address calculation and lookahead, which causes problems such as when branching. When a pipeline disturbance occurs, overhead is generated for filling the pipeline. Furthermore, there is a problem in that the unnecessary passage through the pipeline stage of instructions that do not require fetching of memory operands limits the bus bandwidth available for operand access of instructions that originally require fetching of operands.

In order to solve the above problems, for example, the following patent (Japanese Unexamined Patent Publication No. 1679351/1982) has been filed.

No. 12(2) shows a configuration diagram of the data processing device. In FIG. 12, 18 is an instruction prefetching device for prefetching instruction codes, 19 is an instruction decoding device, and 20 is an address calculation device for calculating addresses of operands.
Reference numeral 21 denotes an operand prereader for prereading operands, 22 an arithmetic control unit, 23 an arithmetic unit, 24 an input/output bus for connecting memory, Ilo, etc., 25 an instruction prereader 18, an operand prereader 21, and operand writing. This is a path control device that mediates requests from the processing device 23 and controls the input/output path 24.

The instruction j game reading device 9 decodes the instruction code prefetched by the instruction prefetching device 18, and if the instruction code is prefetched by the instruction prefetching device 18, it sends a control f1 "i" information for operand address calculation and prefetching if the instruction code is prefetched by the instruction prefetching device 18. In addition, when writing to the memory is performed, a control Jl f+'? information for calculating the address of the operand is issued to the address calculation device 2o.Also, a control fffl regarding a large instruction line] l)'f information is an operation Issued to the control device 22.

The address calculation device 2o calculates the address of the operand, and sends the operand address and control information associated with memory reference to the operand prefetch device 21.

When the operand prefetching device 21 needs to fetch a memory operad, it issues a request to the path nailing device 25, performs prefetching of the memory according to the operand address received from the address calculation device 2o, and queues the read data. .

Additionally, if writing to memory is required, operand addresses are queued. The queuing status of the pre-read data and the write address is notified to the arithmetic control unit 22.

The arithmetic control unit 22 queues the control (MJtri) information for the arithmetic unit 23 received from the instruction decoding device 19. Also, it issues control information in accordance with a request from the arithmetic unit 23. If the control information requires pre-read data or a write address, the state of queuing of the pre-read data and write address in the operand pre-read device 21 is checked.If the preparation is not completed, the control information is sent to the arithmetic unit 23. Issuance of is delayed until the read-ahead data or write address is ready.

The arithmetic device 23 executes arithmetic operations according to the control information received from the arithmetic control device 22 and the prefetch data received from the operand prefetch device 21 . In addition, if it is necessary to write the calculation result to the memory, the bus control device 25
The operation result is written into the memory according to the write address received from the operand prereading device 21.

The operation of the second conventional data processing device configured as described above will be described below.

FIG. 13 shows an operation timing chart.

Instruction prefetching device 18, instruction decoding device 19, address calculation device 20. Instructions being executed in the operand lookahead device 21 and the arithmetic unit 23 are shown in clock units. Here, the instruction prefetching device 18 has an internal cache memory, and the number of installed clocks of each device is as follows: instruction prefetching device 18 (1 clock), instruction decoding BU 19 (1 clock), address calculation device 2o (1 clock), operand The case of the look-ahead device 21 (3 clocks) and the arithmetic device 23 (1 clock) is shown. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of Figure 11, in which an instruction that requires a memory operand fetch is followed by two instructions that do not require a memory operand fetch. , these three instructions are repeated. Specifically, instructions 1 and 4 are instructions that require 7 etches of memory operands, and instructions 2, 3, and 8
6 is an instruction that does not require fetching a memory operand. The initial state of the pipeline is an empty state (for example, at the time of a conditional branch). For the instruction 1, the instruction code is prefetched by the instruction prefetching device 18 at clock t1, and the instruction code is sent to the instruction decoding device 19 in fa. At clock t2, the instruction decoding device 19 decodes the instruction, calculates the address of the operand and issues a prefetch control ml h'7 report to the address calculation device 2o, and issues control information regarding instruction execution to the arithmetic control device 22. . However, since the preparation of the data is not completed, the control information related to instruction execution is queued in the arithmetic control unit 22 and issuance to the arithmetic unit 23 is delayed. Control information for operand address calculation and lookahead; therefore, the clock t
At 3, the address calculation unit 2o calculates the address of the operand, and at clocks t4 to t6, the operand read-ahead unit 21 pre-reads the operand. When the preparation of the data is completed, control information regarding the execution of the instruction queued in the arithmetic control unit 22 is issued and executed in the arithmetic unit 1''123 at the end of the clock.Instruction 2 is executed at clock t2. Look-ahead device 18
The instruction code is prefetched at clock t3, the instruction is decoded by the instruction decoder 19 at clock t3, and only control information regarding instruction execution is issued to the arithmetic control unit 22 since the instruction does not require a 7 etch of the memory operand. However, instruction 1
Since the issuance of the remaining control information has not been completed, the control information for the instruction 2 related to instruction execution is queued in the arithmetic control unit 22, and regular transmission to the arithmetic unit 23 is delayed until clock t8.

According to the second conventional example described above, in instructions such as inter-register operations that do not require fetching of memory operands,
Unnecessary passage through pipeline stages such as operand address calculation and look-ahead is unnecessary, so even if a pipeline disturbance occurs such as at the time of branching, no overhead is generated for filling the pipeline. In addition, bus band limitations for operand access of instructions that originally require seven fetches of operands, which are caused by unnecessary passage through pipeline stages of instructions that do not require fetching of memory operands, are eliminated.

Problem to be Solved by the Invention However, in the above configuration, when an instruction that requires an operation 2nd fetch is followed by an instruction that requires writing to memory, the arithmetic stage of the latter instruction is 011 without using the execution result of the former instruction.
must wait until the operand look-ahead stage and arithmetic stage of the other instruction are completed. Furthermore, if an instruction that does not require an operand fetch or a write to memory follows, the operation stage of that instruction will be able to use the operands of the preceding instruction that requires an operand fetch, without using the execution result of the instruction that requires an operand fetch. It must wait until the read-ahead and arithmetic stages and the arithmetic stages of instructions that require previous writes to memory are completed. Also, when an instruction that requires writing to memory is followed by an instruction that requires operand fetching, the calculation stage of the latter instruction can be used even if the execution result of the former instruction is not used in the calculation. It is necessary to wait until the operand look-ahead stage and operation stage of the I-person's instruction are completed. Furthermore, if an instruction that does not require an operand fetch or a memory write follows, the arithmetic stage of that instruction requires a previous memory write, even if it does not use the execution result of the instruction that requires an operand fetch. It is necessary to wait until the operation stage of the instruction and the operand look-ahead stage and operation stage of the instruction that requires fetching the preceding operand are completed.

In this way, if an instruction that requires an operand fetch and an instruction that requires δ loading to memory occur consecutively in a program, the number of locks to be performed will increase, and the operand fetch for subsequent inter-register operation instructions will also be transferred to memory. The first problem is that the execution of instructions that do not require writing is delayed. This problem will be explained using the operation timing diagram of FIG. 14. The required number of clocks for each device is the same as shown in FIG. However, the queue ink of the write address in the operand lookahead device 21 is 1 clock, and the calculation and writing to the memory in the arithmetic unit 23 is 4 clocks.
Clocks. Figure 14 shows the sequence of instructions as follows:
A case is shown in which an instruction that requires an operand fetch (instruction 1), an instruction that writes a register into memory (instruction 2), and an instruction that does not require operand fetch or writing to memory (instruction 3) follow. Instruction 1 is clock t3
An address is calculated at , an operand is fetched at clocks t4 to t6, and an operation is performed at clock t7. but,
After the address is calculated at clock t4, instruction 2 must wait for the completion of the operation stage of instruction 1, and clock t4
Arithmetic operations and writing to memory are performed from 8 to t11. The operation of instruction 3 is delayed until clock t12.

The present invention takes advantage of these points, and even if an instruction that requires an operand fetch and an instruction that requires writing to memory are consecutive, both instructions can be executed in parallel, and operand fetches such as subsequent inter-register operation instructions can also be executed from memory. Our objective is to provide a data processing device that does not delay the execution of instructions that do not require writing to.

Furthermore, in conventional configurations, once an instruction that requires operand fetching is executed, the calculation stage of subsequent instructions is temporally separated from the instruction lookahead stage, even if the instruction does not require operand fetching. . Therefore, there is a vacancy in the v1 arithmetic stage, and the number of locks performed by the operand fetch fancy instruction that first appears from the empty pipeline is not one clock, and the address calculation device 20 and operand prefetching device 21 Arithmetic device 23
The second problem is that the number of required clocks is the sum of the numbers of clocks. Furthermore, when a conditional branch instruction follows, the instruction prefetch stage of the branch destination instruction is delayed, resulting in a longer pipeline interlock time, resulting in a third problem in that the efficiency of the pipeline is significantly reduced. The second problem can be compared to the operation timing diagram in Figure 15, and the third problem can be compared to the first problem.
This will be explained using the operation timing diagram shown in FIG. In both figures, the required number of clocks for each device is the same as that shown in FIG. Figure 16 shows the instruction sequence: two instructions that do not require operand fetch (instruction 1, instruction 2), followed by one instruction that requires operand fetch (instruction 3), and then two instructions that do not require operand fetch. The case where (instruction 4, instruction 6) continues is shown. Instruction 1 and instruction 2 are operated on clock t3 and clock t4, respectively, but instruction 3 is operated on clock t9 because it is in the address calculation stage and operand prefetch stage. Therefore, during the period from clock t5 to clock t8, there is an empty operation stage, and the number of locks to be performed for instruction 3, which first appears from the empty pipeline and requires operand fetch, is 5 clocks, and the number of locks for instruction 4 and instruction 5 is 5 clocks. The arithmetic stage is separated by six clocks from the instruction lookahead stage. FIG. 16 shows the instruction sequence: one instruction that requires operand fetch (instruction 1) and four instructions that do not require operand fetch (instruction 2 to instruction 5), followed by a conditional branch instruction (
Instruction 6) follows, and a branch is established in conditional branch instruction 6, indicating a case where the branch is taken to an instruction (instruction n) that does not require operand fetching. Instruction 1 skip: Since an address calculation stage and an operand prefetch stage are required, the calculation stages of subsequent instructions 2 to 6 are separated by 6 clocks from the instruction prefetch stage. Therefore, the instruction prefetch stage of the branch destination instruction n is clock t13, and in the instruction prefetch stage, the ;
An interlock of 6 clocks at t12 will occur. As described above, in the conventional configuration, the appearance of conditional branch instructions, which occur at a frequency of 20 cents in a program, causes a significant decrease in the efficiency of the pipeline.

In view of this point, the present invention prevents an empty operation stage from occurring even when an instruction that requires operand lookahead/notch is followed by an instruction that does not require operand fetch, and the first operand fetch that appears from an empty pipeline. Even when the number of locks required to execute a necessary instruction is one clock, and a conditional branch instruction follows, the pipeline interlock time is the same as when there is no instruction requiring operand fetch, and the efficiency of the pipeline is reduced. It is an object of the present invention to provide a data processing device that minimizes degradation.

In addition, in the conventional configuration, when a register that is rewritten by an operation of an instruction that does not require operand fetch is read by the address calculation of a subsequent instruction that requires operand fetch, the address calculation stage is the operation stage of the instruction that does not require operand fetch. The fourth problem is that the pipeline is interlocked until it is completed (this is called address calculation interference), and the efficiency of the pipeline is reduced. This problem will be explained using the operation timing diagram of FIG. 17. The required number of clocks for each device is the same as shown in FIG. Figure 17 shows an instruction sequence that includes an instruction that requires operand fetch (instruction 1), followed by two instructions that do not require operand fetch (instruction 2 and instruction 3), and an instruction that requires operand fetch (instruction 4). continues, and the calculation result of instruction 3 is used in the address calculation of instruction 4.

Address calculation for instruction 4 can be performed at clock t6 if there is no interference in address calculation, but due to interference, instruction 3
The process is made to wait until the next clock t10 when the calculation of is completed.

Thus, in the address calculation stage, interlocks of as many as four clocks t6 to t9 occur in the pipeline, and address calculation interference causes a decrease in pipeline efficiency.

In view of this point, the present invention prevents interlocks from occurring even when a register that is rewritten by an operation of an instruction that does not require operand fetching is read by the address calculation of a subsequent instruction that requires operand fetching, so that the pipeline An object of the present invention is to provide a data processing device that does not reduce efficiency.

In addition, in conventional configurations, when an instruction that requires multiple operand fetches or an instruction that involves writing multiple operands to memory is executed, subsequent instructions may be executed even if no operand fetches are required and Even if the execution result of an instruction that requires fetching operands or writing multiple operands to memory is not required, the operation of that instruction may require fetching multiple operands or writing multiple operands to memory. The sixth problem is that an instruction that involves writing an operand to memory has to wait a long time for completion, which reduces the efficiency of the pipeline. Additionally, in conventional configurations, an instruction that follows an instruction that requires fetching multiple operands or writing multiple operands to memory is an instruction that requires fetching multiple operands or writes multiple operands to memory. The sixth problem is that the performance of the software that optimizes the program cannot be maximized so that the execution results of instructions that involve writing are not required. The fifth and sixth problems will be explained using the operation timing diagram of FIG. 18. The required number of clocks for each device is the same as shown in FIG. 18th
The figure shows an instruction sequence in which an instruction that fetches three operands (instruction 1) is followed by two instructions that do not require operand fetch (instruction 2, instruction 3), and both instructions 2 and 3 are instructions. This shows a case where the execution result of step 1 is not required. Instruction 1 is the first instruction at clocks t4 to t6.
The second operand is prefetched and stored in register R1 at clock t7.The second operand is prefetched at clock t7 to t9 and the operand is stored in register R2 at clock t10. The third operand is read in advance and stored in the register R3 at clock t13. The operation of instruction 2 is performed even though the arithmetic unit 23 is not used at clock t4 and instruction 2 does not use registers R1, R2 and R3, which are the execution results of instruction 1.
The process is awaited until the next clock t14 of the third calculation stage of instruction 1. Furthermore, the operation of instruction 3 was not performed until clock t15 even though the arithmetic unit 23 was not used at clock t6 and instruction 3 did not use registers R1 and R2R3, which were the execution results of instruction 1. be done. In this way, a large amount of idle time is generated in the arithmetic unit 23, and the efficiency of the pipeline is significantly reduced.

In view of this, the present invention provides that even if an instruction that requires fetching multiple operands or an instruction that involves writing multiple operands to memory is executed, the following instruction does not require fetching operands, and If you do not need the execution result of an instruction that requires fetching multiple operands or writing multiple operands to memory, then you can use the instruction that requires fetching multiple operands or writing multiple operands to memory. It is an object of the present invention to provide a data processing device that performs operations in parallel with or in advance of instruction operations that involve writing operands to memory, and that does not reduce pipeline efficiency. Further, the present invention
An instruction that follows an instruction that requires fetching multiple operands or writing multiple operands to memory is the result of executing an instruction that requires fetching multiple operands or writing multiple operands to memory. Reorganize the program so that it does not require
The purpose of this invention is to provide a data processing device that enables the performance of software to be fully utilized.

All of the above-mentioned issues are related to the operand look-ahead device 2.
This becomes more noticeable as the number of clocks required for 1 increases. Therefore, in the conventional configuration, by providing the operand prefetching device 21 with a canon memory for data and reducing the number of clocks required when the operand prefetching device 21 scans the data, the first to sixth problems can be alleviated. It is possible to do so. However, as the capacity of the built-in cache memory increases, the hint rate improves, but the access time to the cache memory increases, making it difficult to reduce the number of clocks required when the operand look-ahead device 21 caches. There was a seventh issue.

In view of this, the present invention provides the first to sixth locks regardless of the increase or decrease in the number of locks required for reading and writing operands depending on whether or not there is a built-in cache memory, the hit rate of the cache memory, the capacity of the cache memory, etc. It is an object of the present invention to provide a data processing device that can solve the problems and also set the number of locks required for reading and arranging operands independently of the number of locks used for inter-register operations.

In addition, in the conventional configuration, in order to shorten the waiting time for pre-read data in the arithmetic control unit 22, the instruction decoder 19 sends the instruction decoding device 19 to the address calculation device 20 as early as possible before sending control information related to instruction execution to the arithmetic control unit 22. It is necessary to send control information for address calculation and lookahead to Therefore, control of the instruction decoding device 19 becomes complicated. Furthermore, the above configuration requires complicated control such as waiting for pre-read data or write addresses in the arithmetic control unit 22. As described above, as the control of each device becomes more complicated, the delay time of the control circuit increases, and the eighth problem is that it is difficult to improve the clock frequency at which the processor operates.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome these problems and provide a data processing device that can easily increase the clock frequency at which a processor operates.

Means for Solving the Problems The first invention includes an instruction prefetching means for prefetching an instruction, an instruction decoding means for decoding the instruction, and an instruction format that reads from or writes to the memory depending on the decoding result. At least a general-purpose register and arithmetic means consisting of an arithmetic unit; and operand reading means for reading operands from the memory according to addresses obtained by the 11n arithmetic means provided exclusively for instructions whose instruction format requires reading from the memory; read operand transfer means for storing data obtained by the operand reading means in a general-purpose register in the arithmetic means; and the arithmetic means provided exclusively for instructions whose instruction format requires writing to memory. and a write operand transfer means for retrieving data to be written into the memory by the operand writing means from a general-purpose register in the arithmetic means. It is a device.

Further, the second invention provides an instruction prefetching means for prefetching an instruction, an instruction decoding means for decoding the instruction, and an instruction format that does not require reading from or writing to the memory according to the solution result. performs the arithmetic operation specified by the instruction, and when the instruction format requires reading from or writing to memory, the controller comprises at least a general-purpose register and an arithmetic unit that calculates the address of the operand to be read or written. an operand reading means for reading an operand from the memory according to an address obtained by the first calculating means, which is provided exclusively for an instruction whose instruction format requires reading from the memory; a second arithmetic means for performing an arithmetic operation on the operand read from the memory in the operand reading means; and a read operation for storing data obtained by the second arithmetic means in a general-purpose register in the first arithmetic means. Operand transfer means and τδ
operand writing means for writing an operand into memory according to an address obtained by said first arithmetic means provided exclusively for instructions whose instruction format requires writing to memory; The data processing device includes write operand transfer means for extracting data to be written from a general-purpose register in the first operation means.

Further, the third invention includes an instruction prefetching means for prefetching an instruction, an instruction decoding means for decoding the instruction, and an instruction format that does not require reading from or writing to the memory according to the decoding result. A single or multiple operand that performs the arithmetic operation specified by the instruction and, if the instruction format requires reading from or writing to memory, performs a calculation operation on the address of the operand to be read or written, and reads from memory. an arithmetic means comprising at least a general-purpose register and an arithmetic unit for issuing information for specifying a general-purpose register storing a single or multiple operands to be stored or written to memory; Operand reading means for reading a single or multiple operands from the memory according to the address obtained by the arithmetic means provided exclusively for instructions requiring reading, and storing the single or multiple operands to be read from the memory. read operand transfer means for receiving information for specifying a general-purpose register from the arithmetic means and storing single or multiple operands obtained by the operand reading means in the general-purpose register in the arithmetic means; Operand writing means for writing a single or multiple operands into memory according to the address obtained by the arithmetic means provided exclusively for instructions requiring writing to the memory; A write operand transfer for receiving information for specifying a stored general-purpose register from the arithmetic means and retrieving single or multiple operands to be written into memory by the operand writing means from the general-purpose register in the arithmetic means. This is a data processing device with 6ja of means.

Further, the fourth invention includes an instruction prefetching means for prefetching an instruction, an instruction decoding means for decoding the instruction, and an instruction format that reads the instruction from the memory or writes to the memory according to the decoding result. A single or multiple operand that performs the arithmetic operation specified by the instruction and, if the instruction format requires reading from or writing to memory, performs a calculation operation on the address of the operand to be read or written, and reads from memory. a first arithmetic means comprising at least a general-purpose register and an arithmetic unit for issuing information for specifying a general-purpose register storing a single or multiple operands to be stored or written to memory; operand reading means for reading single or multiple operands from memory according to an address obtained by said first arithmetic means provided exclusively for instructions requiring reading from memory, and said operand reading means; Receives from the calculation means a second calculation means for performing an operation on the single or multiple operands read from the memory and a general-purpose register for storing the single or multiple operands read from the memory ( τ1 Read operand transfer means for storing single or multiple operands obtained by the second operation means in a general-purpose register in the first operation means, and an instruction whose instruction format requires writing to memory. operand writing means for writing single or multiple operands into memory according to the address obtained by the first arithmetic means provided exclusively for the purpose; and general-purpose operands storing single or multiple operands to be written into memory. write operand transfer means for receiving information for specifying a register from the arithmetic means and retrieving single or multiple operands to be written into memory by the operand writing means from a general-purpose register in the first arithmetic means; It is a data processing device.

'Still, a sixth invention provides a sixth invention in addition to the first or third invention, when an instruction subsequent to an instruction being executed by the operand reading means is being executed by the calculation means, a plurality of execution result flags are issued by the calculation means. Using the generation information, when the operand reading means finishes executing the instruction, the operand reading means 1111 issues a plurality of execution result flag generation information issued by the operand reading means 111, which receives a change due to the execution of a subsequent instruction by the arithmetic means 111. This data processing device includes flag generation means that validates only the flag generation information that was not present and reflects the execution results in a status register that stores a plurality of execution result flags.

Further, a sixth invention is the second or fourth invention, in which when the first calculation means is executing an instruction subsequent to the instruction being executed by the second calculation means, the first calculation means issues an instruction. 1) When the second arithmetic means described in 1) completes instruction execution, the plurality of execution result flag generation information issued by the second arithmetic means described in ml is used. Among them, only the flag generation information that has not been changed by the execution of the subsequent instruction by the first calculation means is made valid;
The present invention is a data processing device that includes flag generation means that reflects execution results in a status register that stores a plurality of execution result flags.

Effects The first and second inventions have the configuration described above, and the first arithmetic means that operate independently of each other executes instructions that do not require operand fetching such as inter-register operations or writing to memory. The read operand transfer means and the second arithmetic means execute an instruction requiring reading of an operand from the memory, and the operand writing means and the write operand transfer means execute an instruction requiring writing of an operand to the memory.

As a result, an instruction that requires an operand fetch and a subsequent operand 7 fetch and an instruction that does not require a write to memory, and an instruction that requires a write to memory and a subsequent operand fetch and a write to memory are not required. Instructions, instructions requiring operand fetch and subsequent instructions requiring writing to memory, and instructions requiring writing to memory and subsequent instructions requiring operand fetch can be executed in parallel.

Further, while the operand reading means, the read operand transfer means, and the second arithmetic means are executing an instruction requiring an operand fetch, the first arithmetic means executes a subsequent instruction that does not require an operand fetch. As a result, even if an instruction that requires operand fetching is followed by an instruction that does not require operand fetching, there will be no empty space in the calculation stage, and the first instruction that requires operand fetching that appears from the empty pipeline will be locked. The number can be one clock.

In addition, since instructions that require operand fetching are executed by the operand reading means, read operand transfer means, and second calculation means independently of the first calculation means, the first calculation stage of subsequent instructions is the instruction prefetch. There will be no time away from the stage. Therefore, even when a conditional branch instruction follows an instruction that requires an operand 7 fetch, the pipeline interlock time can be made equal to the case where no instruction that requires an operand fetch is present, thereby minimizing the decrease in pipeline efficiency. Can be done.

It's a moat, operan for operations between registers! Since operations for instructions that do not require puff etching, as well as address calculations for operands for instructions that require operand fetch and instructions that require writing to memory, are performed in the order of the instruction sequence by the first operation means,
No interlock occurs even when a register that is rewritten by an operation of an instruction that does not require an operand fetch is read by an address calculation of a subsequent instruction that requires an operand fetch or an instruction that requires writing to memory.

In the third and fourth inventions, with the above-described configuration, after the address of an instruction requiring fetching of a plurality of operands is calculated by the first calculation means, the operand reading means, the read operand transfer means, and the second calculation means are processed. It operates and executes multiple times independently of the first calculation means. Further, for an instruction that requires writing multiple operands to memory, after the address is calculated by the first calculation means, the operand writing means and the write operand transfer means operate multiple times independently of the first calculation means. and execute it. As a result, subsequent instructions do not require operand fetching, and
If the execution result of an instruction that requires fetching multiple operands or writing multiple operands to memory is not required, the operation of the instruction may be performed by fetching multiple operands in the first calculation means. It can be performed in parallel or in advance of the operation of a required instruction or instruction that involves writing multiple operands to memory.

Also, 1st, 2nd. According to the third and fourth inventions, the above-described configuration allows the first arithmetic means to execute instructions that do not require operand fetching such as inter-register operations or writing to memory, and the operand reading means and read operand transfer means. The execution of an instruction requiring reading of an operand from the memory by the operand writing means and the write operand transfer means are independent of each other. Therefore, depending on the presence or absence of a built-in cache memory, the cache memory hit rate, the cache memory capacity, etc., the number of locks required to read an operand from memory may increase or decrease, and the number of locks required to write an operand to memory may increase or decrease. Even if it increases or decreases,
The temporal positions of the operation stages of instructions that follow these instructions, such as inter-register operations, that do not require operand fetching or writing to memory remain unchanged.

The first and second inventions do not perform pre-reading of memory operands due to the above-described configuration. Therefore, the instruction decoding means does not need to issue the control information for address calculation prior to the control information regarding instruction execution, and can issue all the control information to the first calculation means at the same time. Therefore, control of the instruction decoding means becomes simple. Further, complicated control such as waiting for pre-read data and write addresses is not required. In this way, the delay time of the control circuit is shortened as the control of each device is simplified, and the clock frequency at which the processor operates can be easily increased.

In the sixth and sixth aspects of the invention, with the above-described configuration, when the first calculation means is executing an instruction subsequent to the instruction being executed by the operand reading means or the second calculation means, the flag generation means is configured to Using a plurality of execution result flag generation information υ issued by the arithmetic means, and when the operand reading means or the second arithmetic means finishes executing the instruction, the plurality of execution result flag generation information issued by the operand reading means or the second arithmetic means are used. Among the execution result flag generation information, only the flag generation information that has not been changed by the execution of the subsequent instruction by the first calculation means is validated, and the execution result is reflected in the status register. Therefore, even if the order of the instructions executed by the first arithmetic means and the operand reading means or the second arithmetic means is different from the order of the instruction sequence of the program, it is the same as if the instructions were executed in the order of the instruction sequence of the program. Consistent flags are reflected in the status register in the processor.

Embodiment FIG. 1 shows a block diagram of a data processing apparatus in an embodiment of the present invention. In FIG. 1, 1 is an instruction prefetching device that prefetches instruction codes; 2 is an instruction decoding device;
3 is a first arithmetic unit; 4 is an operand read unit that reads operands; 5 is a second arithmetic unit; 6 is an operand write unit that writes operands to memory;
Reference numeral 7 designates an input/output path that connects memory, Ilo, etc., and 8 designates a bus control device that arbitrates requests from the instruction prefetch device 1 and the operand read device 4 and controls the input/output bus flow.

The instruction decoding device 2 decodes the instruction code prefetched by the instruction prefetching device 1, and outputs control information related to instruction execution, control information for calculating and reading addresses of operands when memory operands are fetched, and writing to memory. control information for calculating and writing addresses of operands in cases involving .

The first arithmetic unit 3 executes an operation according to the control information received from the instruction decoder 2 when the instruction is an operation between registers or an operation between registers and immediate values.

When an instruction involves a 7-etch of a memory operand, the address of the operand is calculated according to the control information received from the instruction decoding device 2, and the operand address, control information associated with memory reference, and control information regarding instruction execution are sent to the operand reading device 4. do. Further, when the instruction involves writing to the memory, a write address is calculated according to the control information received from the instruction decoder 2, and the write address and control information associated with the memory write are sent to the operand writing device 6.

The operand reading device 4 issues a request to the bus control device 8 and reads the memory according to the operand address received from the first arithmetic device 3.

The read data is sent to the second arithmetic unit 5 together with control information regarding instruction execution.

The second arithmetic unit 6 executes an arithmetic operation according to the data received from the operand reading device 4 and the control information regarding instruction execution, and the result of the arithmetic operation is returned to the first arithmetic unit 3.

The operand writing device 6 takes in the write data from the first arithmetic device 3, issues a request to the bus control i# device 8 through the operand reading device 4, and writes data to the memory according to the write address received from the first arithmetic device 3. Let's do it.

FIG. 2 shows a detailed configuration diagram of the first arithmetic unit 3, operand reading device 4, second arithmetic device 5, and operand writing device 6 shown in FIG.

In FIG. 2, 301 is an arithmetic control circuit that controls the first arithmetic unit 3 according to control information regarding instruction execution and control information for operand address calculation received from the instruction decoder 2, 302 is a general-purpose register, and 3o3 is an arithmetic control circuit. a register control circuit that controls the general-purpose register 302;
04 is a first arithmetic and logic operation circuit that operates on the data stored in the general-purpose register 302, 3o6 is a status register, and 306 is a flag generation circuit that generates flag information of the operation result indicated by the status register 305. It is implemented in the device 3. 401 is a read address register that holds the address for reading memory; 4o2;
receives control information associated with memory reading from the arithmetic control circuit 301, including information (register list) specifying registers to store the results of reading multiple operands;
A read control circuit that controls the operand read device 4 and the register control circuit 303; 403 is a read data buffer that holds read data received from the path control device 8; 404 is a read address that increases the contents of the read address register 401 by a certain value; The above is implemented in the operand reading device 4 with an incremental circuit. A second arithmetic and logic operation circuit 601 performs operations on data stored in the read data buffer 403 and the general-purpose register 302, and is implemented in the second arithmetic unit 6. 601 is a write address register that holds the address for writing to memory; 6o2
is the control HP associated with memory writing, including information (register list) that specifies the registers storing operands when multiple operands are written? The f-information calculation control circuit 301
A write control circuit 603 receives write data from the general-purpose register 302 or holds write data received from the second arithmetic and logic circuit 601. A buffer 604 is a write address increment circuit that increases the contents of the write address register 601 by a fixed value, and the above is implemented in the operand writing device 6. The flag generation circuit 306 receives information regarding flag generation from the first arithmetic and logic operation circuit 304 and the second arithmetic and logic operation circuit 501, and generates a flag.

The operation of the data processing apparatus of this embodiment configured as described above will be described below.

FIG. 3 shows the relationship between instruction types and the flow of pipeline stages. Here, IF is an instruction prefetching stage in the instruction prefetching device 1, DICG is an instruction decoding stage in the instruction decoding device 2, EX1 is the first arithmetic stage in the first arithmetic device 3, and OF is an operand reading stage in the operand reading device 4, EX2 O8 represents the second arithmetic stage in the second arithmetic unit 6, and O8 represents the operand write stage in the operand write device 6. Instructions are prefetched by an instruction prefetch device 1 and decoded by an instruction decoder 2. The flow of subsequent processing varies depending on the type of instruction.

(a) is the case of an inter-register operation instruction or a register/immediate open instruction. The process ends with the calculation in the first calculation device 3. That is, the first arithmetic unit 3 has a general-purpose register 302
data still 'Ji operation Fl; (1 example, the immediate value obtained from the circuit 301 is the first arithmetic theory)] J! It is calculated by the calculation circuit 304 and stored in the general-purpose register 302.

(1)) is an instruction that performs an operation between memory and registers and stores the result in a register; it also includes instructions that do not perform operations. The process starts with address calculation of the operand in the first arithmetic unit 3, readout of the operand in the operand reading unit 4, and calculation in the second arithmetic unit 5, and ends. That is, the first arithmetic unit 3 calculates the read address of the operand using the first arithmetic and logic circuit 304 and sends it to the read address register 401 . The operand reading device 4 passes the read address held in the read address register 401 to the path control device 8.
The read data received from the read data buffer 403 is temporarily held. The second arithmetic unit 6 operates on the read data held in the read data buffer 403 together with the contents of the general-purpose register 302, which is one operand, in the second arithmetic and logic operation circuit 501, and sends the result to the general-purpose register 302.
Store in 02. When the instruction does not involve an operation, the second arithmetic and logic operation circuit 501 functions to pass the contents of the read data buffer 403 as is.

(C) is a case of a (store) instruction that writes the contents of a register to memory. The process ends with calculation of the write address in the first arithmetic unit 3, and writing to the memory in the operand writing devices. That is, the first arithmetic unit 3 calculates the write address of the operand using the first arithmetic and logic circuit 304 and sends it to the write address register 601. Operation 2
The command writing device 6 takes in the write data from the general-purpose register 302, temporarily holds it in the write data buffer 603, and then sends it to the bus control device 8 together with the write address held in the write address register 801, and writes it into the memory.

(d) is an instruction that performs a register-memory operation and writes the result to memory. The memory operand in this case is read → update → write. The processing ends with address calculation of the operand in the first arithmetic unit 3, reading of the operand in the operand reading unit 4, operation in the second arithmetic unit 6, and writing of the operation result in the memory in the operand writing unit 6. . That is, the first arithmetic device 3
The logical operation circuit 304 calculates the read/write address of the operand and sends it to the read address register 401 and the write address register 601. The operand reading device 4 passes the read address held in the read address register 401 to the bus control device 8.
The read data received from the read data buffer 403 is temporarily held. The second arithmetic unit 5 operates on the read data held in the read data buffer 74o3 together with the contents of the general-purpose register 302, which is one operand, in the second arithmetic and logic operation circuit 501, and stores the result in the write data buffer 603. The operand writing device e is
Both the write address held in the write address register 601 and the write data held in the write data buffer 603 are sent to the bus control device 8 to write into the memory.

(6) is an instruction that performs an operation between a plurality of memory operands and registers having consecutive addresses and stores a plurality of results in a plurality of registers. It also includes instructions that do not require arithmetic operations (multiple load).

The process ends by repeating the address calculation of the first memory operand in the first arithmetic unit 3, the reading of the operand in the operand reading unit 4, and the operation in the second arithmetic unit 6. However, the reading of the next operand by the operand reading device 4 and the calculation by the second arithmetic device 6 are executed in parallel. That is, the Wj1 arithmetic unit 3 is the first arithmetic logic operation circuit 3.
At step 04, the read address of the first operand is calculated and sent to the read address register 401, and a register list indicating the register group in which the result is to be stored is sent from the arithmetic control circuit 301 to the read control circuit 402.

Also, at this time, the register control circuit 303 controls the general-purpose register 3
Prohibits reading of the register group storing the result of 02 j1-. The operand reading device 4 transfers the read address held in the read address register 401 to the bus control device 8.
At the same time, the address is incremented by a certain value in the read address increment circuit 404 and held in the read address register 401 again. The read data received from the bus control device 8 is temporarily held in the read data buffer 403. The second arithmetic unit 6 operates on the read data held in the read data buffer 403 together with the contents of the general-purpose register 302, which is one operand, in the second arithmetic and logic operation circuit 601, and stores the result in the general-purpose register 302. When the instruction does not involve an operation, the second arithmetic and logic operation circuit 601 functions to pass the contents of the read data buffer 403 as is. At the same time, the read control circuit 402
03 is notified that one of the results has been stored in the general-purpose register 302, and in response to this, the register control circuit 303 releases the prohibition of reading of that register in the general-purpose register 302. For the second and subsequent operands, the operand reading device 4 and the second arithmetic device 5 independently of the first arithmetic device 3 perform incremental addition of the operand address, read out the memory operand, perform the operation, store the result, and perform the operations in the corresponding register. Repeatedly cancel the read prohibition. At this time, the operand reading device 4 and the second arithmetic device 6 form a pipeline and execute in parallel.

(f') is a case of an instruction (multiple store) that writes the contents of a plurality of registers to memories with consecutive addresses. The process ends after the first arithmetic unit 3 calculates the write address of the first register, and then the operand write unit 6 repeats writing to the memory.

That is, the first arithmetic unit 3 has a first arithmetic logic operation circuit 304.
calculates the write address of the first operand and sends it to the write address register 601, and also sends a register list indicating the register group to be written to the memory to the arithmetic control circuit 30.
1 to the write control circuit 602. Also, at this time, the register control circuit 303 prohibits writing of the register group to the memory of the general-purpose register 302. The operand writing device 6 writes the general-purpose register 3 according to the writing control circuit 602.
After reading the write data from 02 and temporarily holding it in the write data buffer 7603, the write address register 6
bus controller 8 with the write address held at 01.
At the same time as writing into the memory, the write address increment circuit 604 increments the address by a certain value and holds it in the write address register 601 again. At the same time, the write control circuit 602 notifies the register control circuit 303 that one of the registers is held in the write data buffer 7603, and the register control circuit 303 receives this and prohibits writing to that register in the general-purpose register 302. Release. For the second and subsequent operands, the operand writing device 6 independently of the first arithmetic device 3 reads the register, adds the operand address incrementally, writes it to the memory,
Repeatedly cancel the write prohibition of the register.

As described above, in the data processing device of this embodiment, the first arithmetic unit 3 disconnects the subsequent processing, and the operand reading device 4
The second arithmetic unit 5 or operand writing device 6 executes subsequent processing of the instruction independently of the instruction prefetch unit 1, instruction decoder 2, and first arithmetic unit 3.

FIG. 4 shows an operation timing chart.

instruction prefetching device 1, instruction decoding device 2, first arithmetic device 3,
The instructions being executed in the operand reading device 4 and the second arithmetic unit 6 and changes in the contents of the status register 306 are shown in units of clocks. Here, the instruction prefetching device 18 has an internal cache memory, and the number of clocks required for each device is the instruction prefetching device 1 (1 clock).
, instruction decoding device 2 (1 clock), first arithmetic unit 3 (1 clock),
clock), operand reading device 4 (3 clocks),
and the case of the second arithmetic unit 5 (one clock) is shown. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. 13, in which a memory-register operation register storage instruction is followed by two inter-register operation instructions; These three commands are repeated.

Specifically, instruction 1.4 is a memory-register operation register storage instruction, and instruction 2.3.5.6 is an inter-register operation instruction. The initial state of the pipeline is an empty state (for example, at the time of a conditional branch). The instruction code of the instruction 1 is prefetched by the instruction prefetching device 1 at clock t1, and the instruction code is issued to the instruction decoding device 2. At clock t2, the instruction decoding device 2 decodes the instruction, and issues control information for operand address calculation and readout and control information regarding instruction execution to the first arithmetic device 3. Control HI for operand address calculation and reading? According to the f-report, the first arithmetic unit 3 is activated at clock t3.
The address calculation of the operand is performed at clock t4.
From t6 to t6, the operand reading device 4 reads out the operand. The read data and control information regarding instruction execution are sent to the second arithmetic unit 6 and are operated by the second arithmetic unit 5 at clock t7. For the instruction 2, the instruction code is prefetched by the instruction prefetching device 1 at clock t2, the instruction is decoded by the instruction decoding device 2 at clock t3, and only control information related to instruction execution is issued to the first arithmetic device 3.

The calculation is performed by the first calculation device 3 at clock t4. Similarly, instruction 3 is operated by first arithmetic unit 3 at clock t6.

Thus, instruction 2. Instruction 3 is operated in advance of instruction 1, and instruction 5 is operated in parallel with instruction 1. The flag generation circuit 306 generates a flag for instruction 2 based on information obtained from the first arithmetic and logic circuit 304 at clock t4, and reflects it in the status register 305 at clock t6. At this time, the flag updated by the bird is memorized. Furthermore, at clock t5, a flag for instruction 3 is generated based on information obtained from the first arithmetic and logic circuit 304, and is reflected in the status register 306 at clock t6. At this time as well, the updated flag is memorized. Next, at clock t7, the flag generation circuit 306 generates a flag for instruction 6 based on information obtained from the first arithmetic and logic operation circuit 304, and generates a flag for instruction 1 based on information obtained from the second arithmetic and logic operation circuit 501. generate. However, at this time, the instruction 1 flag is not generated. Also, if there is a flag updated by instruction 6 that is the same as the flag updated by instruction 1, instruction 5 is generated with priority even if it is the same as the flag updated by clocks ts and te. . The generated flag is reflected in the status register 305 at clock t8.

As described above, according to this embodiment, the order in which instructions are operated does not necessarily match the order of the program. However, by arbitrating the flags generated by the flag generating circuit 306, the flag can be reflected in the status register 305 consistent with the case where the instructions are operated in the order of the program.

FIG. 6 shows an operation timing diagram explaining that this embodiment solves the first problem. The required number of clocks for each device is the same as shown in FIG. However, the number of clocks required for writing to the memory in the operand tracing device is three clocks. The instructions being executed are the same as the instruction sequence shown in the operation timing diagram in Figure 14, including the memory-register operation register store instruction (instruction 1), register transfer to memory (store ) instruction (instruction 2) and an inter-register operation instruction (instruction 3) are shown.

In the instruction 1, an address is calculated at clock t3, an operand is fetched at clocks t4 to t6, and an operation is performed at clock t7. However, after the address of instruction 2 is calculated by the first arithmetic unit 3 at clock t4, the subsequent processing is separated, and the operand writing unit 6 transfers the register to the memory independently of the first arithmetic unit 3. go to That is, the operand writing device 6 writes write data from the general-purpose register 302 to the write data buffer 603 at clock t6.
At clocks t7 to t9, the write address held in the write address register 601 and the write data held in the write data buffer eo3Vc are sent to the bus control device 8, and written into the memory. Instruction 3 is operated at clock t6 in parallel with the memory reading of instruction 1 and the memory writing of instruction 2.

As described above, according to this embodiment, one instruction that requires an operand fetch, an instruction that does not require an operand 7 fetch or a -1rF write to memory, an instruction that requires writing to memory, and a subsequent operand Instructions that require neither a fetch nor a write to memory, instructions that require an operand fetch followed by a write to memory, and instructions that require a write to memory followed by an operand fetch. Each instruction can be executed in parallel, and the execution time of a sequence of instructions can be shortened.

FIG. 8 shows an operation timing diagram explaining that this embodiment solves the second problem. The required number of clocks for each device is the same as shown in the fourth section. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of Fig. 15, in which two inter-register operation instructions (instruction 1, instruction 2) are followed by one memory inter-register operation register. A case is shown in which a store instruction (instruction 3) is followed by two inter-register operation instructions (instruction 4 and instruction 6). In instruction 3, address calculation is performed at clock t5, operands are read from the memory at clocks t6 to t8, and operated at clock t9. However, since the operand reading device 4 and the second arithmetic device 6 operate independently of the first arithmetic device 3, the instruction 4. Instruction 5 is executed in parallel with the memory reading of instruction 3 at clock t6. It can be calculated using clock t7,
Pipeline stage vacancies do not occur.

As described above, according to this embodiment, even if an instruction that requires operand fetching is followed by an instruction that does not require operand fetching, there is no vacancy in the operation stage, and the first operand fetch that appears from the empty pipeline is The number of locks required to execute the necessary instructions can be set to one clock.

FIG. 7 shows an operation timing diagram explaining that this embodiment solves the third problem. The required number of clocks for each device is the same as shown in FIG. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG.
Inter-register operation Register storage instruction (instruction 1) and four inter-register operation instructions (instruction 2 to instruction 6) are followed by a conditional branch instruction (instruction 6), and in conditional branch instruction 6, a branch is taken and the inter-register operation is executed. This shows the case of branching to an instruction (instruction n). Instruction 1 requires address calculation of the operand and reading of the operand from memory, but since the operand reading device 4 and the second arithmetic device 6 operate independently of the first arithmetic device 3, instructions from the subsequent instruction 2 6 is command 1
The first arithmetic unit 3 can perform calculations from clock t4 to clock t8 in parallel with the reading of the memory.

Therefore, the instruction prefetch stage of one branch destination instruction n is advanced to clock t9, and in the instruction prefetch stage, the pipeline only generates an interlock of two clocks, clocks t7 to t8.

As described above, according to this embodiment, even when an instruction requiring an operand fetch is followed by a conditional branch instruction, the pipeline interlock time is made the same as when there is no instruction requiring an operand fetch, and the pipeline Efficiency loss can be minimized.

FIG. 8 shows an operation timing diagram explaining that this embodiment solves the fourth problem. The required number of clocks for each device u1 is the same as that shown in FIG. The instruction sequence being executed is the same as the instruction sequence shown in the operation timing diagram of FIG. 2. Instruction 3) is followed by a memory-register calculation register storage instruction (instruction 4), and the calculation result of instruction 3 is used in the address calculation of instruction 4. Since both the address calculation and the inter-register operation are performed in the first arithmetic unit 3, the address calculation for instruction 4 can be performed at the next clock t6 when the operation for instruction 3 is completed, and the pipeline interlock due to address calculation interference can be avoided. Does not occur.

As described above, according to this embodiment, even when a register that is rewritten by an operation of an instruction that does not require an operand fetch is read by the 71'tz calculation of an instruction that requires an operand fetch, no interlock occurs. Therefore, the efficiency of the pipeline can be prevented from decreasing.

FIG. 9 shows that this embodiment is the 6th. This is an operation timing diagram illustrating solving the sixth problem. The required number of clocks for each device is the same as shown in FIG.

The instruction sequence being executed is the same as the instruction nocence shown in the operation timing diagram of Figure 18, and includes an instruction (multiple load) that transfers three memory operands with consecutive addresses to three registers (instruction 1). , two inter-register operation instructions (instruction 2, instruction 3) follow, and instruction 2. Instruction 3 shows a case where the execution result of instruction 1 is not required. Instruction 1 is clock t4-t6
The first operand is read out at clock t7, and the operand is stored in register R1 at clock t7.
At t9, the second operand is read and clock t1
0, the operand is stored in the register R2, the third operand is read out at clocks t10 to t12, and the operand is stored in the register R3 at clock t13. However, after the first arithmetic unit 3 calculates the address of the first operand at clock t3, the operand reading unit 4 and the second arithmetic unit 5 operate independently of the first arithmetic unit 3, so that the subsequent instructions 2 - Instruction 3 can be operated on clock t4 and clock t6 in first arithmetic unit 3 in parallel with the memory reading and register storage of instruction 1.

Therefore, the first arithmetic unit 3 does not have a long idle time required for memory reading.

The same is true for instructions that write the contents of multiple registers to memory with consecutive addresses (multiple store).
After the first arithmetic unit 3 calculates the address of the first operand, the operand writing device 6 operates independently of the first arithmetic unit 3, and subsequent instructions write the contents of multiple registers at consecutive addresses. The first arithmetic unit 3 can perform calculations in parallel with the writing of the instruction to the memory. Therefore, the first arithmetic unit 3 does not have a long idle time required for memory writing.

As described above, according to this embodiment, even if an instruction that requires multiple operand fetches or an instruction that involves writing multiple operands to memory is executed, the following instructions do not require operand fetching and can be executed. , and if the execution result of an instruction that requires fetching multiple operands or writing multiple operands to memory is not required, then the operation of that instruction requires fetching multiple operands. It is possible to avoid reducing the efficiency of the pipeline by performing the operation in parallel with or in advance of the operation of an instruction that involves writing an instruction or a plurality of operands to memory.

Further, according to this embodiment, an instruction that follows an instruction that requires fetching multiple operands or an instruction that involves writing multiple operands to memory writes an instruction that requires fetching multiple operands or writes multiple operands The performance of software that optimizes programs can be maximized so that the execution results of instructions that involve writing are not required.

Next, it will be explained that this embodiment solves the seventh problem. In the data processing device of this embodiment configured as described above, after the first arithmetic unit 3 calculates the address of the operand, the subsequent processing is separated, and the operand reading device 4
, the second arithmetic unit 5, and the operand writing device 6 are operated independently of the first arithmetic unit 3, so that subsequent instructions can be operated in the first arithmetic unit 3 in parallel with memory reading and writing. As a result, even if the required number of clocks of the operand reading device 4 or the operand writing device 6 increases, the calculation stage of an instruction following an instruction involving memory reading or writing will not be delayed. It also has a built-in cache memory for data.
Operand reading device 4 or operand writing device 6
Even if the required number of clocks is reduced, the temporal position of the arithmetic stage of an instruction following an instruction involving a memory read or write does not change.

As described above, according to this actual example, it is necessary to read operands and include IIF depending on the presence or absence of built-in Canon Yu memory, cache memory hit rate, cache memory capacity, etc., regardless of the increase or decrease in the number of locks. , 1st to 6th
In addition, the number of locks required for reading and writing operands can be set independently of the number of locks required for inter-register operations.

Finally, it will be explained that this embodiment solves the eighth problem. The data processing device of this embodiment configured as described above does not read ahead of the memory operand. Therefore, the instruction decoding device 2 does not need to issue control information for address calculation prior to control information related to instruction execution, and can issue all control information to the first arithmetic device 3 at the same time.

Therefore, control of the instruction decoding device 2 becomes simple. Further, there is no need for complicated control such as look-ahead data or waiting for addresses including -3.

As described above, according to this embodiment, the delay time of the control circuit is shortened as the control of each device is simplified, and the clock frequency at which the processor operates can be easily increased.

Note that in this embodiment, when executing an instruction (load or multiple load) that reads a single or multiple operands from memory and stores them in a register without performing an operation, the contents of the read data buffer 403 are directly transferred to the second arithmetic logic. Although the data is passed through the arithmetic circuit 501 and stored in the general-purpose register 302, it is also possible to provide a data line leading directly from the read data buffer 403 to the general-purpose register 302 and store the data in the general-purpose register 302. By doing this,
Load instructions and multiple load instructions that occur frequently in a program no longer require a second arithmetic stage, reducing pipeline interlocks that occur when the execution results of these instructions are used in subsequent instructions, and improving pipeline efficiency. This has the effect of improving. However, when the flag is changed by a load instruction or a multiple load instruction, it is necessary to send information regarding flag generation from the read data buffer 403 to the flag generation circuit 306.

In addition, although this embodiment did not consider the address translation mechanism for real memory, in the case of virtual memory, the instruction prefetch device 1, operand read device 4, or path control device 8
An address translation mechanism may be incorporated into the address translation mechanism.

Further, in this embodiment, the operand reading device 4 and the second arithmetic device 5 are separated, but they may be realized as a single device as the operand reading device.

Further, in this embodiment, each device has been described as one pipeline stage, but it may be realized as a device having a plurality of pipeline stages.

As described in detail, according to the first and second inventions, an instruction requiring an operand fetch, a subsequent instruction requiring neither an operand fetch nor writing to memory, and a subsequent instruction requiring writing to memory are provided. Instructions followed by instructions that do not require an operand fetch or write to memory; Instructions that require an operand fetch followed by instructions that require a memory write; Instructions that require a memory write followed by an operand fetch Each of the necessary instructions can be executed in parallel, and the execution time of the instruction sequence can be shortened.

In addition, even if an instruction that requires operand fetching is followed by an instruction that does not require operand fetching, there will be no empty space in the calculation stage, and the number of locks to be executed for the first instruction that requires operand fetching that appears from the empty pipeline will be reduced to 1. It can be a clock.

However, even when a conditional branch instruction follows an instruction that requires an operand fetch, the pipeline interlock time is the same as when there is no instruction that requires an operand fetch, thereby minimizing the decrease in pipeline efficiency. can.

Even if a register that is rewritten by an instruction that does not require an operand fetch is read by the address calculation of a subsequent instruction that requires an operand fetch or an instruction that requires writing to memory, no interlock occurs and the pipeline efficiency is not reduced.

As explained above, according to the third and fourth inventions, even if an instruction that requires fetching multiple operands or an instruction that involves JF storing multiple operands into memory is executed, If the following instruction does not require an operand fetch and does not require the execution result of an instruction that requires fetching multiple operands or writing multiple operands to memory, the operation of that instruction is , can be performed in parallel with or in advance of an instruction that requires fetching multiple operands or writing multiple operands to memory, thereby preventing deterioration in pipeline efficiency. Further, according to the present invention, an instruction that follows an instruction that requires fetching multiple operands or writing multiple operands to memory is an instruction that requires fetching multiple operands or writes multiple operands to memory. The performance of the software that optimizes BLOGRANO can be maximized so that the execution results of instructions that involve writing are not required.

Also, 1st. Second. According to the third and fourth inventions, even if the number of locks required to read one operand from the memory increases or decreases depending on the presence or absence of a built-in cache memory, the hit rate of the cache memory, the capacity of the cache memory, etc. The above effect will be maintained even if the number of locks required for writing to is increased or decreased. Further, the number of locks required for operand reading and writing can be set independently of the number of locks required for executing inter-register operations.

According to the first and second inventions, the delay time of the control circuit can be shortened by simplifying the control of each device, and the clock frequency at which the processor operates can be easily increased.

Further, according to the sixth and sixth inventions, even if the order of executed instructions is different from the order of the instruction sequence of the program, a flag that is consistent with the case where the instructions are executed in the order of the instruction sequence of the program is set in the processor. can be reflected in the status register.

As shown above, the practical effects of the present invention are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a data processing device in an embodiment of the present invention, and FIG. 2 is a detailed configuration diagram of the first arithmetic unit 3, operand reading device 4, second arithmetic device 6, and operand writing device 6 of the same embodiment. , FIG. 3 is a diagram of the relationship between instruction types and pipeline stages of the same embodiment, FIG. 4 is an operation timing diagram of the same embodiment, and FIG. 6 is a diagram of the same embodiment explaining how to solve the first problem. 6 is an operation timing diagram of the same embodiment to explain solving the second problem, and FIG. 7 is an operation timing diagram of the same embodiment to explain solving the third problem. , FIG. 8 is an operation timing diagram of the same embodiment to explain solving the fourth problem, and FIG. 9 is an operation timing diagram of the same embodiment to explain solving the sixth and sixth problems. Timing diagrams, FIG. 10 is a configuration diagram of a first conventional data processing device, FIG. 11 is an operation timing diagram of the first conventional example, FIG. 12 is a configuration diagram of a second conventional data processing device, FIG. 13 is an operation timing diagram of the second conventional example, and FIG. 14 is a diagram of the second conventional example ψj, which explains the first problem.
16 is an operation timing diagram of the second conventional example to explain the second problem. FIG. 16 is an operation timing diagram of the second conventional example to explain the third problem. FIG. 17 is an operation timing chart of the second conventional example to explain the fourth problem, and FIG. 18 is an operation timing diagram of the second conventional example to explain the fifth and sixth problems. 1... Instruction prereading device, 2... Instruction decoding device, 3... First arithmetic unit, 4... Operand reading device, 5... Second Arithmetic device, 6.
... Operand writing device, 7 ... Input/output bus, 8 ... Bus system (incorporated) device, 301 ...
... Arithmetic sterilization circuit, 302 ... General purpose register, 3
03...Register control circuit, 304...
First arithmetic logic operation circuit, 305...Status register, 306...Flag generation circuit, 401...
...Read address register, 402...
・Read control circuit, 4o3...Read data buffer, 404...Read address increment circuit, 601
...? 1S2 arithmetic and logic operation round, 601...
...Write address register, 602..., 1':
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Claims (1)

[Scope of Claims] (1) Instruction prefetching means for prefetching instructions, instruction decoding means for decoding instructions, and an instruction format that does not require reading from or writing to memory depending on the decoding result. It consists of at least a general-purpose register and an arithmetic unit that performs the arithmetic operation specified by the instruction, and when the instruction format requires reading from or writing to memory, calculates the address of the operand to be read or written. an arithmetic means, and an operand read means for reading an operand from the memory according to an address obtained by the arithmetic means, which is provided exclusively for an instruction whose instruction format requires reading from the memory, and the operand read means. A read operand transfer means for storing the obtained data in a general-purpose register in the arithmetic means, and an address obtained by the arithmetic means provided exclusively for instructions whose instruction format requires writing to memory. operand writing means for writing an operand into memory according to the operand writing means; and write operand transfer means for retrieving data to be written into the memory by the operand writing means from a general-purpose register in the arithmetic means; During the execution of an instruction that requires reading from the memory, the arithmetic means executes a subsequent instruction that does not require reading from or writing to the memory in parallel, and the operand writing means requires writing to the memory. During the execution of the instruction, the arithmetic means executes a subsequent instruction that does not require reading from or writing to the memory in parallel, and the operand reading means also executes an instruction that requires reading from the memory. (2) an instruction prefetching device for prefetching an instruction; an instruction decoding means for decoding the instruction format; and, depending on the decoding result, if the instruction format does not require reading from or writing to the memory, performs the arithmetic operation specified by the instruction; a first arithmetic means comprising at least a general-purpose register and an arithmetic unit, which performs an address calculation operation of an operand to be read or written when writing is required;
Further, an operand reading means for reading an operand from the memory according to an address obtained by the first arithmetic means provided exclusively for an instruction whose instruction format requires reading from the memory, and a memory in the operand reading means. a read operand transfer means for storing data obtained by the second arithmetic means in a general-purpose register in the first arithmetic means;
Operand writing means whose instruction format writes an operand into memory according to the address obtained by the first calculating means; write operand transfer means for retrieving from a register, the operand reading means and the second arithmetic means performing an instruction that requires reading from the memory, the first arithmetic means subsequently reading from the memory; executing instructions that do not require reading or writing to the memory in parallel; and while the operand writing means is executing an instruction that requires writing to the memory, the first arithmetic means subsequently reads from the memory; Alternatively, instructions that do not require writing to memory are executed in parallel, and furthermore, while the operand reading means and the second arithmetic means are executing an instruction that requires reading from memory, the operand writing means is executed in parallel. Alternatively, a data processing device is characterized in that instructions that require preceding writing to memory are executed in parallel. (2) An instruction prefetching means for prefetching an instruction, an instruction decoding means for decoding an instruction, and an instruction that specifies when the instruction format does not require reading from or writing to the memory according to the decoding result. When an arithmetic operation is performed and the instruction format requires reading from or writing to memory, the address of the operand to be read or written is calculated, and the single or multiple operands to be read from memory are stored. Alternatively, an arithmetic means consisting of at least a general-purpose register and an arithmetic unit that issues information for specifying a general-purpose register storing a single or multiple operands to be written to memory, and an instruction format that requires reading from memory. specifies an operand reading means for reading a single or multiple operands from the memory according to an address obtained by the arithmetic means provided exclusively for the instruction to be read from the memory, and a general-purpose register for storing the single or multiple operands to be read from the memory. read operand transfer means for receiving information from the operation means to store the single or multiple operands obtained by the operand read means in a general-purpose register in the operation means; Operand writing means for writing a single or multiple operands into memory according to the address obtained by the arithmetic means provided exclusively for the required instruction, and storing the single or multiple operands to be written to the memory. write operand transfer means for receiving information for specifying a general-purpose register from the arithmetic means and retrieving single or multiple operands to be written into memory by the operand writing means from the general-purpose register in the arithmetic means; While the operand reading means is executing an instruction requiring reading from memory of a single or multiple operands, the arithmetic means performs in parallel execution of an instruction that does not require subsequent reading from or writing to memory, In addition, while the operand writing means is executing an instruction that requires writing a single or multiple operands to memory, the arithmetic means can perform a subsequent read from memory or execution of an instruction that does not require writing to memory in parallel. and furthermore, during execution of an instruction in which said operand reading means requires reading a single or multiple operands from memory, said operand writing means requires writing subsequent or preceding single or multiple operands to memory. A data processing device characterized in that it executes instructions in parallel. (4) Instruction prefetching means for prefetching instructions, instruction decoding means for decoding instructions, and instructions specifying when the instruction format does not require reading from or writing to memory according to the decoding results. When an arithmetic operation is performed and the instruction format requires reading from or writing to memory, the address of the operand to be read or written is calculated, and the single or multiple operands to be read from memory are stored. Alternatively, a first arithmetic means consisting of at least a general-purpose register and an arithmetic unit that issues information for specifying a general-purpose register storing a single or multiple operands to be written to memory, and further an instruction format for reading from memory. operand reading means for reading single or multiple operands from memory according to the address obtained by the first arithmetic means provided exclusively for instructions requiring a second arithmetic means for performing an arithmetic operation on a single or multiple operands, and information for specifying a general-purpose register for storing a single or multiple operands to be read from memory from the arithmetic means; read operand transfer means for storing the obtained single or multiple operands in a general-purpose register in the first arithmetic means; operand writing means for writing a single or multiple operands into memory according to the address obtained by the first arithmetic means; and information for specifying a general-purpose register storing the single or multiple operands to be written to memory; write operand transfer means for retrieving single or multiple operands received from the arithmetic means and written to memory by the operand write means from a general purpose register in the first arithmetic means;
During the execution of an instruction in which the operand reading means and the second arithmetic means require reading a single or multiple operands from memory, the first arithmetic means performs subsequent reading from or writing to memory. carrying out the execution of instructions not required in parallel, and during the execution of an instruction requiring writing of a single or multiple operands to memory by the operand writing means, the first arithmetic means subsequently reading from the memory; The execution of instructions that do not require writing to memory is performed in parallel; 1. A data processing device, characterized in that operand writing means executes in parallel instructions that require writing subsequent or preceding single or multiple operands into memory. (5) When an instruction subsequent to the instruction being executed by the operand reading means is being executed by the calculation means, the operand reading means executes the instruction using a plurality of execution result flag generation information issued by the calculation means. When terminating the process, among the plurality of execution result flag generation information issued by the operand reading means, only the flag generation information that has not been changed by the execution of the subsequent instruction by the arithmetic means is validated, and the plurality of execution result flags are 4. The data processing apparatus according to claim 1, further comprising a flag generating means for reflecting an execution result in a status register to be stored. (6) When the first arithmetic means is executing an instruction subsequent to the instruction being executed by the second arithmetic means, using a plurality of execution result flag generation information issued by the first arithmetic means, When the second arithmetic means finishes executing an instruction, the plurality of execution result flag generation information issued by the second arithmetic means is not changed by the execution of a subsequent instruction by the first arithmetic means. 5. The data processing apparatus according to claim 2, further comprising flag generation means for validating only the flag generation information obtained by the execution result and reflecting the execution result to a status register storing a plurality of execution result flags.