JP2002342301A - Microcomputer provided with coprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer with which data processed by a coprocessor can be outputted to the outside at a high speed. SOLUTION: The microcomputer is composed of a CPU, which is connected to an internal system bus, for receiving a program from a memory through the internal system bus and running this program, the coprocessor for performing prescribed arithmetic/control according to an instruction outputted from the CPU, an external bus I/F part for performing data transfer with an external chip, and a dedicated bus provided independently of the internal system bus for connecting the coprocessor and the external bus I/F part, and the coprocessor directly transfers the arithmetic result through the dedicated bus to the external bus I/F part so that data can be transferred from the coprocessor to the external chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a microcomputer having a coprocessor for transferring data to and from an external chip, and a system using the same.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a microcomputer having a conventional coprocessor. In this example, the microcomputer 10 is a CPU 1 that executes a program.
And a coprocessor 2 for performing special operations and control, an external bus I / F unit 3 for transferring data to and from the external chip 4, and a built-in peripheral circuit 6. The CPU 1 and the coprocessor 2
Are connected by a coprocessor I / F, and a CPU 1, an external bus I / F unit 3 and a built-in peripheral circuit 6 are connected to an internal system bus 7
Connected by The microcomputer is connected to the external chip 4 through the external bus 9 by the external bus I / F unit 3.

The external bus I / F 3 transfers data from the internal system bus to the external bus 9 or from the external bus 9 to the internal system bus. When transferring the data processed by the coprocessor 2 to the external chip 4, the CPU 1
Reads the data processed by the coprocessor 2 into an internal register via the coprocessor I / F. afterwards,
The data is transferred to the external bus I via the internal system bus.
/ F5, and the external bus I / F5 transfers to the external chip 4 via the external bus 9.

[0004]

However, the operating frequency of the internal system bus is often lower than that of the CPU 1 or the coprocessor 2, and the internal system bus is occupied by other built-in peripheral circuits 6. In some cases, it was difficult to transfer the processing data of the coprocessor 2 to the external chip 4 at high speed.

The data processed by the coprocessor 2 is temporarily read into a register of the internal CPU 1 via a coprocessor I / F, and then the data is transferred to an external bus I / F 5 via an internal system bus. Since the transfer is performed, and the external bus I / F 5 is further transferred to the external chip 4 via the external bus 9, there is a limit in improving the transfer speed.

Accordingly, an object of the present invention is to provide a coprocessor 2
To provide a microcomputer capable of outputting the data processed in step (1) to the outside at high speed.

[0007]

SUMMARY OF THE INVENTION The present invention (claim 1) provides:
An internal system bus, a memory connected to the internal system bus and storing a program, and a CP connected to the internal system bus and receiving the program from the memory via the internal system bus and executing the program
U, a coprocessor connected to the CPU and performing a predetermined operation and control in accordance with a command output from the CPU, an external bus I / F unit for transferring data to and from an external chip; An external bus I / F unit is connected to the external bus I / F unit, and a dedicated bus is provided independently of the internal system bus. The coprocessor transmits the operation result to the external bus I / F unit via the dedicated bus. And a data transfer from the coprocessor to the external chip is performed by providing a microcomputer computer provided with a coprocessor.

The present invention (claim 2) provides the microcomputer according to claim 1, wherein the CPU and the coprocessor are connected by a coprocessor I / F.

According to a third aspect of the present invention, in the first aspect, the CPU, the coprocessor, and the external bus I
/ F unit, the memory, the internal system bus, and the external bus I / F unit are integrated on one semiconductor chip.

The present invention (claim 4) according to claim 1, further comprising a memory controller for controlling the memory, wherein the CPU, the coprocessor, the external bus I / F unit, the memory controller, and the internal The system bus and the external bus I / F unit are integrated on one semiconductor chip, the memory is mounted on another chip, and connected to the internal system bus via the memory controller. A microcomputer is provided.

The present invention (claim 5) provides the microcomputer according to claim 1, further comprising a built-in peripheral circuit connected to the internal system bus.

According to a sixth aspect of the present invention, in the first aspect, the external bus I / F section includes,
A microcomputer is also provided which is also connected to the internal system bus.

According to a seventh aspect of the present invention, in the first aspect, the external bus I / F unit includes a first data holding buffer for holding data transferred from the dedicated bus, and the internal system. A microcomputer provided with a second data holding buffer for holding data transferred from a bus.

The present invention (claim 8) is characterized in that, in the above-mentioned claim 1, the microcomputer functions as an image processing circuit, the coprocessor is a geometry processor, and the external chip is an image processor. The microcomputer provided as follows.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment A microcomputer 100 according to a first embodiment of the present invention.
Is shown in FIG. This microcomputer includes a CPU 101 that executes a program.
And an external bus I / F unit 103 for transferring data to and from the external chip 104, a built-in peripheral circuit 106, and a memory 105 for storing programs and data. . CPU
101 and coprocessor 102 are coprocessor I / F 10
8. CPU 101, external bus I /
The F unit 103, the built-in peripheral circuit 106, and the memory 105 are connected by an internal system bus 107, and the coprocessor 102 and the external bus I / F unit 103 are connected by a dedicated bus 110.

The microcomputer is connected to an external chip 104 via an external bus 109 by an external bus I / F unit 103. The external bus I / F is C
The data from the PU 101 is received via the internal system bus 107, and the external chip 10 is received via the external bus 109.
Transfer to 4. On the other hand, the external bus I / F receives data from the coprocessor 102 via the dedicated bus 110 and transfers the data to the external chip 104 via the external bus 109.

Similarly, the external bus I / F receives data from the external chip 104 via the external bus 109 and transfers the data to the CPU 101 via the internal system bus 107. On the other hand, the external bus I / F section
Can be received via the external bus 109 and transferred to the coprocessor 102 via the dedicated bus 110. Specific examples of the built-in peripheral circuit 106 include a DMA controller, a timer, and a serial interface such as a UART.

The program includes coprocessor instructions to be processed by the coprocessor. When the coprocessor instructions are read from the memory 105, the CPU 101 transfers the coprocessor instructions to the coprocessor, and executes the processing. Ask the processor. The processing result is sent to the CPU 101
Are used to be output to the CPU 101, but those to be output to the outside are directly output to the external bus I / F section 103 by the dedicated bus 110, and are output to the external bus I / F 103.
The processing result is transferred to the external chip 104 through the / F unit 103 and the external bus 109. Coprocessor instructions include:
An instruction for outputting the operation result to the CPU 101 and an instruction for outputting the operation result to the external bus I / F unit 103 exist separately.

Generally, the internal system bus 107 is a general-purpose one to which the memory 105, the built-in peripheral circuit 106 and the CPU 101 are connected, and has a relatively low speed. If the DMA controller is in use, the processing may be delayed due to contention, such as waiting for the processing to be completed and then obtaining the right to use the internal system bus 107 by the CPU 101. However, since the data transfer is performed between the coprocessor and the external bus I / F unit 103 via the dedicated bus 110, high-speed transfer without delay is possible.

FIG. 2 is a block diagram showing a configuration example of the external bus I / F unit. In this example, dedicated bus 1
10 is connected to the data holding buffer 111, and the internal system bus is connected to the data holding buffer 112. The dedicated bus 110 has a high bus speed for performing high-speed data transfer, whereas the internal system bus has a relatively low bus speed. here,
In order to enable high-speed data transfer from the dedicated bus 110, the data holding buffer 112 has a FIFO structure, and enables continuous transmission and reception of data.

(2) Embodiment 2 FIG. 3 shows a block diagram of a microcomputer according to Embodiment 2 of the present invention. Here, the microcomputer 200 is implemented as an image processing circuit. The microcomputer includes a CPU 201 for executing a graphics processing program, a geometry processor 202 as a coprocessor for performing graphics processing such as setting up polygons, and an image processing processor 20 for performing rendering and the like as an external chip.
4, an external bus I / F unit 203 for transferring data to and from the built-in peripheral circuit 206 and a memory 21 for accessing an external main memory 216 for storing programs and data.
It consists of six controllers. The CPU 201 and the geometry processor 202 are connected by an I / F 208. The CPU 201, the external bus I / F unit 203, the built-in peripheral circuit 206, and the memory 216 are connected by an internal system bus 207, and the geometry processor 202 and the external bus I / F unit 203 are connected by a dedicated bus 210. The image processor 204 is connected to a graphics memory including a frame memory, and constructs an image to be displayed. A monitor constituted by a CRT or LCD receives the contents of the frame memory and displays it.

The microcomputer is connected to an image processor 204 via an external bus 209 via an external bus I / F unit 203. External bus I / F
The data from the CPU 201 is stored in the internal system bus 2
07, and transferred to the image processor 204 via the external bus 209. On the other hand, external bus I / F
The unit receives data from the geometry processor 202 via the dedicated bus 210 and transfers the data to the image processor 204 via the external bus 209.

Similarly, the external bus I / F receives data from the image processor 204 via the external bus 209, and receives the data from the CPU 2 via the internal system bus 207.
Transfer to 01. On the other hand, the external bus I / F unit can also receive data from the image processing processor 204 via the external bus 209 and transfer the data to the geometry processor 202 via the dedicated bus 210. Specific examples of the built-in peripheral circuit 206 include a DMA controller, a timer, and a serial interface such as a UART.

The graphics processing program contains instructions to be processed by the image processor 204 such as matrix operation and product-sum operation. When such an image processing instruction is read from the memory 216, the CPU 201 executes the image processing. Transfer instructions to the geometry processor. The processing result is sent directly to the external bus I / F by the dedicated bus 210.
The processing result is transferred to the image processor 204 via the external bus I / F unit 203 and the external bus 209.

Generally, image processing instructions need to process very large data. On the other hand, the internal system bus 2
07 is a memory 216, a built-in peripheral circuit 206 and a CP.
It is a general-purpose device to which U201 is connected, and has a relatively low speed. If the DMA controller is in use, the CPU 201 waits until the processing is completed before the CPU 201
May obtain the right to use the internal system bus 207, and the processing may be delayed due to contention. But,
The geometry processor and the external bus I / F unit 203
Since data transfer is performed by the dedicated bus 210, high-speed transfer without delay is possible. Therefore, it is possible to display a favorable moving image without dropping frames.

In one embodiment, CPU 201 and the geometry processor operate at 200 MHz and CPU 2
01 and the I / F 208 between the geometry processor is also 200
Drive at MHz. The internal system bus 207, dedicated bus 210, and external bus are each driven at 100 MHz. However, in some cases, it is desirable to drive the dedicated bus 210 at a higher speed and at 200 MHz in consideration of the capacity of the geometry processor, other timings, and the like.

FIG. 4 is a block diagram showing a configuration example of the external bus I / F unit. Also in this example, dedicated bus 2
10 is connected to the data holding buffer, and the internal system bus 207 is connected to the data holding buffer. The dedicated bus 210 has a high bus speed for performing high-speed data transfer, whereas the internal system bus 207 has a relatively low bus speed. Here, in order to enable high-speed data transfer from the dedicated bus 210, the data holding buffer has a FIFO structure.
It enables continuous data transmission and reception. In particular, in order to transfer data to the image processing processor 204 without delay while the calculation is being performed by the geometry processor 202, eight 4-byte registers are provided.

Although the present invention has been described in detail with reference to the embodiments, it is apparent to those skilled in the art that the present invention is not limited to the embodiments described in the present application. The device of the present invention can be embodied as modifications and alterations without departing from the spirit and scope of the present invention defined by the claims. Therefore, the description of the present application is intended for illustrative purposes, and has no restrictive meaning to the present invention.

For example, in the above embodiment, the coprocessor is connected to the CPU and the dedicated bus, but not to the internal system bus. However, it is also possible to receive coprocessor instructions from the CPU and read the necessary data directly from memory via the internal system bus. In such a case, the coprocessor and the internal system bus are connected by the I / F 320 as in the microcomputer 300 shown in FIG.

[0030]

As described above, the microcomputer according to the present invention has the following effects.

(1) Since the coprocessor and the external bus I / F are connected by a dedicated bus independent of the internal system bus, data processed by the coprocessor can be output to the outside at high speed.

(2) Since the internal system bus is not used while the coprocessor is outputting data to the outside at a high speed via the dedicated bus, the CPU can perform another process using the internal system bus. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an external bus I / F unit of the microcomputer according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a microcomputer according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of an external bus I / F unit of a microcomputer according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a modification of the microcomputer according to the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating an example of a microcomputer including a conventional coprocessor.

[Explanation of symbols]

 1 CPU 2 coprocessor 3 external bus I / F unit 4 external chip 6 built-in peripheral circuit 7 internal system bus 9 external bus 101 CPU 102 coprocessor 103 external bus I / F unit 104 external chip 105 memory 106 built-in peripheral circuit 109 external bus Reference Signs List 100 microcomputer 110 dedicated bus 111 data holding buffer 112 data holding buffer (FIFO) 200 microcomputer 202 geometry processor 203 external bus I / F unit 204 image processor 206 built-in peripheral circuit 207 internal system bus 210 dedicated bus 216 external main memory 201 CPU 300 microcomputer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G06F 15/16 620 G06F 15/16 620G 640 640B F-term (Reference) 5B013 DD03 5B045 AA01 BB12 BB14 BB36 GG09 KK08 5B062 AA03 CC04 CC05 DD02 DD10 EE10 FF05 5B077 AA18 BA02 DD02

Claims (8)

[Claims] 1. An internal system bus, a memory connected to the internal system bus and storing a program, and a memory connected to the internal system bus and receiving and executing the program from the memory via the internal system bus A CPU connected to the CPU, a coprocessor that performs a predetermined operation and control in accordance with a command output from the CPU, an external bus I / F unit that performs data transfer with an external chip, The external bus I / F
And a dedicated bus provided independently of the internal system bus, and the coprocessor directly transfers the operation result to the external bus I / F via the dedicated bus. A microcomputer computer having a coprocessor, whereby data is transferred from the coprocessor to the external chip. 2. The microcomputer according to claim 1, wherein the CPU and the coprocessor are connected by a coprocessor I / F. 3. The semiconductor device according to claim 2, wherein the CPU, the coprocessor, the external bus I / F, the memory, the internal system bus, and the external bus I / F are integrated on one semiconductor chip. The microcomputer according to claim 1. 4. A memory controller for controlling the memory, wherein the CPU, the coprocessor, the external bus I / F unit, the memory controller, the internal system bus, and the external bus I / F unit are one. 2. A memory integrated on a semiconductor chip, wherein the memory is mounted on a separate chip and connected to the internal system bus via the memory controller.
The microcomputer according to 1. 5. The microcomputer according to claim 1, further comprising a built-in peripheral circuit connected to said internal system bus. 6. The microcomputer according to claim 1, wherein the external bus I / F is connected to the internal system bus together with the dedicated bus. 7. The external bus I / F section includes a first data holding buffer for holding data transferred from the dedicated bus, and a second data holding buffer for holding data transferred from the internal system bus. The microcomputer according to claim 1, further comprising a data holding buffer. 8. The microcomputer according to claim 1, wherein the microcomputer functions as an image processing circuit, the coprocessor is a geometry processor, and the external chip is an image processing processor.