JPH02297594A - Data processor - Google Patents

Abstract

PURPOSE:To execute a large quantity of arithmetic operation at high speed by providing an architecture for executing a large quantity of arithmetic operation at high speed in a digital signal processor. CONSTITUTION:A single chip microcomputer 1 is obtained by integrating a CPU 2 functioning as a microprocessor, the digital signal processor 3 having a floating point arithmetic operation function for performing outline font development, a direct memory access controller 6 having a data block transfer control function, a dual port RAM 4 and a peripheral circuit 7 on one semiconductor substrate. The digital signal processor 3 has the architecture for executing a large quantity of arithmetic operation at high speed. Thus, a large quantity of arithmetic operation is executed at high speed without largely loading the microprocessor.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device, for example, a page printer such as a laser beam printer, a liquid crystal printer, or an LED printer, or a display device using a CRT, plasma, liquid crystal, etc. The present invention relates to a technology that is effective when applied to a microcomputer for developing outline fonts for bitmap displays.

[Prior art]

An example of the expression format of font data used to draw a pattern in a bitmap memory is a dot font format in which a pattern is expressed as a dot matrix. In this dot font format, the font data itself is expressed in a pixel-corresponding dot matrix format, so the data is easy to handle, and patterns based on the font data can be drawn at high speed. However, if the rotation to an arbitrary angle is slow and the dot density is low, the outline of the pattern will become uneven when enlarged and displayed, and if the dot density is increased, the amount of data will increase significantly.

Therefore, by adopting a technique such as so-called vector-I-le graphics, which draws based on outline font data that has a data structure in which the outline of a pattern is defined as a set of lines, the outline of the pattern becomes uneven. It is possible to solve the problem of increasing the amount of data or increasing the amount of data.

For example, the above outline font data includes information indicating the type of line, such as a short line vector, circular arc, spline curve, free curve such as Belair curve, or straight line, as well as information on its point, end point, and other control points. The outline of the font is defined.

When a conventional single-chip microcomputer is used in a system that draws outline fonts based on such outline font data, the CP of the single-chip microcomputer including a direct memory access controller and other peripheral circuits.
The U (Central Processing Unit) core receives data indicating what kind of straight lines or curves the outline font consists of from an external memory containing outline font data, and the CPU core decodes the outline font data. The CPU core performs calculations to develop into a dot pattern, and temporarily develops the corresponding outline font in an external work memory that functions as a font cache. Then, a direct memory access controller with a data block transfer function such as BITBLT (Bit Block Transfer) built into the CPU core itself or a single-chip microcomputer transfers the outline font from work memory to page memory such as frame buffer memory. Transfer to. This completes drawing the outline font to the page memory.0 For example, when printing the drawn content, a drawing/display processor such as a CRT (cathode ray tube) controller draws the completed outline font onto the page memory. etc., is sent to the laser beam printer engine as a video signal.

An example of a document related to this type of outline font drawing system is Nikkei Electronics N11417 (March 23, 1987) published by Nikkei McGraw-Hill.
There are 211 pages.

[Problem to be solved by the invention]

The above-mentioned conventional technology has a problem in that since the CPU core develops the outline font, the CPU core cannot perform other tasks during that time, resulting in a decrease in the operating efficiency of the system. Developing an outline font requires calculating the coordinates of a free curve, which requires a large amount of floating-point operations, and in addition, coordinate transformations such as enlarging, shrinking, and rotating the font, which also require a large amount of floating-point operations, are usually required. This is because the load on the CPU becomes too large because the data has to be streamed.

There are also systems that try to speed up free curve calculations and coordinate transformations by adding an FPU (floating point unit), which is a coprocessor, to the CPU, but the current FPU's calculation speed is limited by its architecture. Each floating point operation takes several microseconds to more than ten JAS, and there is a limit to the speed of calculation. Furthermore, the FPU, which functions as a coprocessor and is tightly coupled to the CPU, executes coprocessor instructions that are mixed with the main processor instructions, so when the FPU is performing floating-point operations, the CPU can execute them in parallel. It is not possible to proceed with independent data processing. In other words, the CPU as the main processor uses an instruction synchronization mechanism to know whether the FPU as a coprocessor is currently executing an instruction, so that the main processor cannot execute new instructions until the FPtJ completes execution of the coprocessor instruction. Do not execute the command 5 CP like this
U is not free to do other work while FPU is developing outline fonts,
In the end, the operating efficiency of the system does not improve much.

An object of the present invention is to provide a data processing device that can perform a large amount of calculations at high speed without placing a large burden on a microprocessor or restricting its operation too much.

Another object of the present invention is to provide a data processing device that can efficiently develop outline fonts.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a data processing device is constructed by including a microprocessor and a digital signal processing processor whose operation is instructed by the microprocessor on one semiconductor substrate.

When storing calculation results etc. by the digital signal processing processor mentioned above in RAM, in order to avoid conflict between the operation and bus access by the microprocessor, it is necessary to use separate buses from both the digital signal processing processor and the microprocessor. It would be nice to see dual port RAM accessible via the .

The configuration including the microprocessor, digital signal processor, and dual port RAM can also be configured as a multi-chip system on a wiring board instead of as a system on a chip.

When using the above system-on-chip or multi-chip data processing device for outline font development, the outline font data is stored in the control memory built in the digital signal processor in the form of a dot pattern in the dual port RAM. May include data processing algorithms for deployment.

Considering that the information developed in the dual-port RAM is transferred to the frame buffer memory or page memory for drawing, blocks of data are transferred to a shared bus that connects one access port of the dual-port RAM and the microprocessor. It is recommended to connect a direct memory access controller that can control transfer.

Furthermore, in order to use the dual port RAM as a font cache memory, it is desirable that the microprocessor be provided with an area for holding information indicating the type of outline font that the microprocessor has instructed the digital signal processor to develop. .

[For production]

According to the above means, the digital signal processing processor included in the data processing device includes an architecture for executing a large amount of operations at high speed, for example, a multiplier and an adder for cumulative multiplication, and also includes a multiplier and an adder for cumulative multiplication. By performing parallel pipeline processing of instruction fetch, data transfer, and calculation by separating the transfer system, the required calculations can be executed faster than when using a coprocessor such as an FPU, and this makes it possible to perform the required calculations faster than when using a coprocessor such as an FPU. A device that includes a microprocessor is better than a device that only includes a microprocessor.
Alternatively, it is possible to execute a large amount of operations at a higher speed than a data processing device including a microprocessor and a coprocessor such as an FPU.

Further, the digital signal processor operates in such a way that it can perform a series of data processing on its own in parallel with the data processing operations of the microprocessor using data processing algorithms stored in a built-in control memory according to instructions from the microprocessor. In other words, a digital signal processing processor has an instruction execution procedure that executes coprocessor instructions mixed with microprocessor instructions instead of microprocessor processing, such as an FPU that is considered a microprocessor. Since it has a control procedure different from that of the microprocessor, data processing can proceed independently of the operation of the microprocessor. This allows the microprocessor to proceed with unrelated or separate processing while the digital signal processor is processing data such as floating point operations, which places a large burden on the microprocessor. It is possible to perform a large amount of calculations at high speed without overloading the microprocessor, and without restricting the operation of the microprocessor too much.

The dual-port RAM, which is provided so that it can be accessed by both the microprocessor and the digital signal processor via separate buses, is used to store calculation results by the digital signal processor, for example, to develop an outline font in the RAM. The microprocessor operates via a dedicated bus separate from the shared bus to which it is coupled, which ensures complete parallel operation between the microprocessor and the digital signal processing processor, and allows processing such as outline font expansion. Increase the efficiency of data processing by digital signal processing processors.

By using the dual port RAM as a font cache memory, there is no need to newly expand the fonts 1 to 1, which have already been expanded and held in the dual port RAM.

When drawing a dot pattern in the frame buffer memory or page memory through outline font expansion, not only memory write operations but also memory read operations are performed to fill in the outline font and perform pixel logic operations during outline font expansion. When it is necessary to create a font for a frame buffer memory or page memory, first expand the Audiline font in dual-port RAM, which can be accessed faster than the frame buffer memory or page memory, create the necessary font, and then write the font all at once to the frame. Transferring data to a buffer memory, etc. means that pixel logical operations are performed to develop outline fonts directly on the page memory or frame buffer memory, and memory read and write operations are performed to fill the interior after development. This works to reduce the overall number of reads and writes to a relatively slow frame buffer memory, etc., compared to the case where data is repeatedly read and written. In other words, it is only necessary to write access to the relatively slow frame buffer memory or page memory in order to transfer the font created in the dual port RAM.

This reduces the processing time until the final drawing is completed.

The direct memory access controller described above improves the efficiency of such data transfers from dual port RAM to frame buffer memory and page memory. If such a direct memory access controller is provided, even if internal filling in the outline phone 1 or pixel logic operations during outline font development are not performed, the final drawing is completed in the frame buffer memory etc. The processing time is shortened.

A dual port RAM used as a work area such as a font cache, etc. can be used with a microprocessor and a digital signal processing processor that can be accessed from different buses, and if necessary, a direct access memory controller, together with the dual port RAM. Being formed on the same semiconductor substrate means that the digital signal processing processor can speed up dual-port RAM access for font development, as well as dual-port RAM for filling processing of developed fonts.
A microprocessor or a digital signal processing processor can use dual-port 6 [Embodiment] (Single-chip microcomputer) Figure 1 shows a single-chip microcomputer that is an embodiment of the present invention. A block diagram of a computer is shown. The single-chip microcomputer 1 shown in the figure includes, but is not particularly limited to, a CPU 2 as a microprocessor, a digital signal processing processor (hereinafter simply referred to as DSP) 3 having a floating point arithmetic function for performing outline font development, A direct memory access controller (hereinafter simply referred to as DMAC) 6 that has a data block transfer control function such as a bit block transfer, a dual port RAM 4, and a ROM that stores the operating program of the CPU 2 and performs data communication with the outside. A peripheral circuit 7 including a serial communication interface controller (hereinafter simply referred to as SCI) for carrying out the operation is integrated on one semiconductor substrate.

Each of the above circuit blocks is commonly connected to an internal bus 5 such as a common bus, and further connected to a DSP 3 and a dual port RAM.
4 are connected by a dedicated bus 13.

The CPU 2 reads and decodes instructions from the operating program in the ROM included in the peripheral circuit 7, and generates various control signals necessary for operations, data transfer, etc. to execute the instructions.

The DSP 3 has a micro ROM in which a data processing algorithm is programmed with micro instructions, although it is not particularly limited.
It is designed to read microinstructions from and control the built-in product-sum calculator, memory, input/output circuit, etc. Such D
SP3 performs high-speed operations such as arithmetic-add operations that occur frequently in floating-point operations, and multiplications that are processed by software on general-purpose microprocessors in order to achieve high-speed data transfer and high processing power. It has multipliers, multiply-accumulate units, etc. for hardware implementation, and has an architecture that enables parallel bibliographic processing of instruction fetches, data transfers, and operations by separating the instruction transfer system and data transfer system. In this embodiment, the data processing algorithms written in the micro ROM include, for example, development of outline fonts, expansion, reduction, and movement of outline fonts.

It has contents for coordinate transformation such as rotation, filling inside the expanded font, etc.

Although the dual port RAM 4 is not particularly limited,
Used as a work area for developing and creating outline fonts. In order to make this dual port RAM4 available as font cache memory, the CP
U2 includes a work area 2 for holding information indicating the type of outline font formed on the dual port RAM 4, which the CPU instructs the DSP 3 to develop.
A is provided. Therefore, CPU2 is
When expanding a line font, by referring to work area 2, you can create two identical outline fonts.
This saves you the trouble of deploying it multiple times. In this way, the processing method for using the dual port RAM 4 also as a font cache memory is selected by the operating program of the CPU 2.

(Outline font drawing system) FIG. 2 shows an example of an outline font drawing system using the single-chip microcomputer 1 described above. The system shown in the figure is an example applied to a laser beam printer (hereinafter simply referred to as LBP), although it is not particularly limited.

The single-chip microcomputer 1 includes a memory 9 for storing font data, a page memory 10 for drawing characters and figures, and a drawing/display processor 11 for drawing figures and sending a video signal to a printer engine 12, etc. Connected to bus 8. The drawing/display processor 11 is ACRTC (HD63484-4, HD63484) manufactured by Hitachi, Ltd.
-6, HD63484-8), etc.

The 1~line font data stored in the memory 9 is not limited to any particular type, but as shown in FIG. Operation code specification area ○Pc containing code information assigned to each operation code, and operands containing coordinate information such as control points required when defining the starting point and end point of a line specified by the code information, as well as free curves, etc. Specified field O
It has a format 1- constituted by PR as a minimum unit. For example, the outline of a character or symbol composed of a plurality of curves or straight lines is defined by a set of outline font data that defines the individual line segments included therein. Such various outline font I-data are stored in the memory 9 for each character and symbol. Examples are provided step by step.

When the CPU 2 attempts to draw a required outline font in the page memory 10, the outline font data constituting the outline phone l- is transferred from the external memory 9 to the DSP 3 to the DMAC 6 as shown in FIG. 3A. Alternatively, the DSP 3 itself may directly import the outline font data from the memory 9.

When using the DMAC6, the CP tJ 2 is set in advance to the initial setting of the transfer source address and the number of transfer words of the memory 9 in the M A C6.If the DSP3 itself accesses the memory 9, the outline to be developed is The CPU 2 provides the DSP 3 with an outline font expansion command including information specifying a font.

Next, the DSP 3 takes in the outline font data as shown in Figure 3B, executes a series of calculations such as calculation of free curves that make up the outline font and coordinate transformation according to its own program, and generates the data as shown in Figure 3C. Then, the font is expanded into the dual port RAM 4 according to the calculation result. The developed font data is data that constitutes a dot pattern. At this time, the DSP 3 may execute filling/filling inside the outline font.

Alternatively, the drawing/display processor 11 may perform filling later.

The outline font developed in the dual port RAM 4 is sent to the external page memory 10 by the DMAC 6 having a bit block transfer function as shown in FIG. 3D. Finally, the document consisting of characters transferred to the page memory 10 and figures drawn by the drawing/display processor 11 is transferred to the drawing/display processor I as shown in FIG. 3E.
The page memory 1o is sent as a video signal to the LBP printer engine 12 by J, and is used for printing.

During the operating period shown in FIGS. 3A-3E, C
PU2 is basically not involved in the development/drawing of outline fonts, except for the initial settings of DSP3 and DMAC6. Therefore, during this time, CPU2 is
Communication with an external post computer (not shown) and Po sent from the host computer.
Since page description languages such as 5t:5script can be decoded, the operating efficiency of the system is improved.

It goes without saying that the DSP 3 can also be used to execute coordinate transformations and the like associated with the deciphering of the page description language by the CPU 2.

(Outline font development and transfer format) As described above, the outline font development and transfer format for dual port RAM 4 is as follows:
Please expand the font for one character in AM4 (see Figure 4A)
, then the DMA C 6 not only transfers the font to the page memory 10 in bit blocks (see FIG. 4B), but also transfers the font to the dual port RAM 4 virtually as shown in FIGS. 5A and 5B. Divide it into two areas, and while the font is being developed in one area, the phono 1 that is being expanded in the other area is DM A.
A format in which the C6 transfers a bit block to the page memory 10 may be adopted. If we adopt the latter method, D
Since SP3 and DMAC6 can operate simultaneously, the efficiency of outline font drawing is higher overall than the former.

(Connection mode between DSP and dual port RAM) In FIG. 6, DSP
A mode in which a dual port RAM 4 is connected to 3 is shown. The DSP 3 shown in FIG. 6 includes, but is not particularly limited to, an arithmetic logic unit in addition to a multiplier or a product-sum unit as an execution unit that can perform addition, multiplication, product-sum operations, etc. at high speed. A computing unit 18, a plurality of registers 17, and a data memory 16 used as a work area are connected by an internal bus 21, and a program memory 1 such as a micro ROM in which data processing algorithms are written.
4, and includes a microsequencer 15 that sequentially reads instructions from the program memory 14 and controls the operation of the execution section. Instructions for accessing data memory 16 in DSP 3 are contained in program memory 14 . This umbrella includes an addressing field for specifying the access address of data memory 16. When the program memory 14 does not contain instructions for directly accessing the dual port 1-RAM 4 external to the DSI'3, the DSP
3 is provided with an address pointer 19 and a data buffer 2o, and the dual port RAM 4 is connected through these. As a result, for the DSP 3, access to the dual port RAM 4 is apparently equivalent to register access to the address pointer 19 and data buffer 20. Therefore, when configuring the DSP3 using an existing DSP module, it is possible to configure the dual port RA without significantly changing the contents of the program memory.
M4 connection becomes possible.

If the program memory 14 includes instructions for directly accessing the dual port RAM 4, it is possible to connect the dual port RAM 4 directly to the internal bus 21 of the DS i) 3 as shown in FIG. can.

That is, the connection is similar to that of the data memory 16 shown in FIG. In this case, the contents of the program memory in the existing DSP module must be changed relatively significantly, but the address pointer 19 and data buffer 20
Since there is no need to go through registers such as , etc., access to the dual port RAM 4 by the DSP 3 becomes faster.

(Dual Port RAM) FIG. 8 shows an example of a dual port RAM having two completely independent access ports. A plurality of memory cells are arranged in a matrix in the memory cell array 30 of this dual port RAM 4. Each memory cell has two sets of memory cell selection terminals and data input/output terminals.

One selection terminal of each memory cell is coupled to a word line that is driven to a selection level according to the decoding result of the address signal 32 by the address decoder 31, and the other selection terminal of the memory cell is connected to the word line driven to the selection level according to the result of decoding the address signal 32 by the address decoder 31. Another word line is coupled which is driven to a select level according to the decoding of signal 34. Further, one data input/output terminal of each memory cell is coupled to a bit line leading to a column selection circuit 35 whose switch is controlled according to the result of decoding the address signal 32 by the address decoder 31, and the data input/output terminal of the other memory cell The output terminal is coupled to another bit line leading to a column selection circuit 36 whose switch is controlled according to the result of decoding the address signal 34 by the address decoder 33. The above column selection time v! 35 is connected to one data input/output circuit 38 via a common data line 37, and the column selection circuit 36 is connected to the other data input/output circuit 40 via a common data line 39.

The address signal 32 is transmitted via the internal bus 5 to CPtJ.
2 and DMAC 6, and the data input/output circuit 38 exchanges data 41 with them. Further, the address signal 34 is given from the DSP 3 via the dedicated bus J3, and the other data input/output circuit 40 exchanges data 42 with the DSP.

As is clear from the above explanation, the dual port RAM shown in FIG. 8 can be read and written completely independently from the internal bus 5 side and the dedicated bus 13 side, but the When write accesses are made at timings where addresses overlap, writing from either one is given priority. Such priority control is carried out by the controller 4 which functions as an arbiter.
4 will do it. This controller 44 receives an address signal R/ws, a chip select signal C8, which is applied via the internal bus 5, an address signal 34, a read/write signal R/Wx3, which is applied via the dedicated bus 13,
Chip select signal CS1. Receive.

The priority control and operation mode and timing control are performed according to these states.1 For example, a wait signal WAIT is used as a control signal related to the priority control.

WA I T1. and enable signals Es and E are generated. The wait signals WAIT, , WADT□, are activated by the DSP3. CPU2 or DMAC
This signal is considered to be a signal instructing the extension of the access cycle of the dual port RAM 4 by 6. Further, the enable signal Es+E>3 is activated by the address decoder 31 and the data output circuit 38 in response to its assert-1 to state.
．． The address decoder 33 and the data input/output circuit 40 are controlled to be operable.

The controller 44 that generates the control signal for such priority control includes the CPU 2 or the DMA C6 and the DSP 3.
When the same address of the dual-port RAM is accessed at the same time by both sides, the wait signal WAI
T, negates wait signal WA I T1. is asserted, the enable signal E5 is asserted, and the enable signal E is negated to initially allow write access from the internal bus 5 side. In other cases, parallel access from both sides is allowed.

The use of the dual port RAM 4, which can be accessed completely independently and in parallel, is particularly effective for developing and transferring outline fonts as explained in FIGS. 5A and 5B.

FIG. 9 shows a dual-port RAM 4 having a structure that utilizes the single-port RAM 50.

In order to use the single port RAM 50 and make it accessible from both internal buses 5 and 13, which are different from each other, one address input circuit of the single port R and AM 50 has one
The output terminals of the pair of buffers 51 and 52 are commonly connected, and the input terminal of one buffer 51 receives the address signal 32, and the input terminal of the other buffer 52 receives the address signal 3.
Supply 4. Furthermore, the output terminal of a buffer 53 for exchanging data 41 and the output terminal of a buffer 54 for exchanging data 42 are commonly connected to one data input/output circuit of the single port RAM 50. Dual port RAM that utilizes single port 50
Since parallel access from both buses 5 and 13 is impossible due to the nature of the bus, arbitration logic is built into the controller 55 to avoid access conflicts from both sides. The controller 55 outputs the wait signals WAIT, , WAIT□ and the enable signals E, E, according to the arbitration logic.
, E1. However, wait signals WA I T, WA I T1 . Ya buffer 51
~54 are controlled.

The dual port RAM 4, which is made by reusing such a single port RAM 50, cannot be accessed in parallel from both ports. The structure of the RAM itself is simplified in terms of the number of selection circuits, etc., and the cost of the dual-port RAM can be reduced.

(Multi-chip computer) The above CPU2. DSP3. Dual port RAM4, D
The MAC 6, peripheral circuit 7, etc. are not limited to being formed on-chip on one semiconductor substrate, but can be actually formed on one wiring board 60 to form a multi-chip computer as shown in FIG. be able to. At this time, on the wiring board 60, there is an outline font data memory 9.L for configuring an outline font drawing system. Page memory 10, drawing/display processor 1
1 etc. can also be implemented. Even in such a multi-chip configuration, if the access time of the dual port RAM 4 can be made sufficiently fast, it is possible to obtain almost the same processing speed as when using a single-chip microcomputer 1 configured in an on-chip format.

In particular, if a necessary data processing device is constructed by using multi-chips on a board, it is possible to easily obtain the desired data processing device without the need to develop a new LSI such as the single-chip microcomputer 1.

(Multiprocessorization of DSP) In the explanation so far, only one DSP3 is placed in a microcomputer or system configured with an LSI or board, but it is possible to make a DSP multiprocessor by using multiple DSP3s. can be achieved.

FIG. 12A shows an example in which one CPU 2 is provided with two sets of DSP 3 and dual baud 1" RAM 4.

In such a configuration, the processing capacity for development to phono 1 is approximately 2
Improve twice as much.

FIG. 12B shows a dedicated DSP 3 for each of the two CPUs 2.
An example is shown in which a dual port 1-RAM is provided.

In this configuration, not only the processing capacity for font development is improved, but also the burden on the CPU 2 for each font development, font drawing, etc. is reduced compared to the example shown in FIG. 1.2A.

In Fig. 12c, there are two sets of DSPs in two c P U 2.
3 and dual port RAM 4 are shared. Compared to FIG. 12B, such a configuration makes it easier to improve the operating efficiency while providing flexibility in the system control operation of the CPU 2.

(Effects of Examples) According to the above embodiment, the following effects can be obtained.

(1,) The DSP3 includes an architecture for executing a large amount of operations at high speed, such as multipliers and adders for cumulative multiplication, and also includes instruction fetch, data transfer, and operations by separating data and instruction transfer systems. By performing parallel pipeline processing of than DSP3 and CP
Using U2 allows faster outline font drawing.

(2) The DSP 3 uses the data processing algorithm in the program memory 14 according to instructions from the CPU 2 to execute a series of data processing such as font development in parallel with the data processing operations of the CPU 2.

In other words, the DSP 3 has an instruction execution procedure that executes coprocessor instructions written mixed with CPU 2 instructions in place of CPU 2 processing, such as an FPU that is considered to be a coprocessor of CPU 2. Since the CPU 2 has a different control procedure, data processing can proceed independently of the operation of the CPU 2. Thereby, when the DSP 3 is performing data processing such as floating point calculation, the CPU 2 can proceed with unrelated or different processing. In this way, the DSP 3 can perform a large amount of calculations at high speed without placing a large burden on the CPU 2 and without restricting the operation of the CPU 2 too much.

(3) The dual port RAM 4, which is provided so that it can be accessed separately from both the CPU 2 and the DSP 3 via different buses, allows the CPU to store calculation results by the DSP 3, for example, to develop an outline font in the RAM.
The CPU 2 and the D S
Complete parallel operation with P3 is guaranteed, and not only data processing such as outline font development by DSP3, but also the operational efficiency of the entire system can be increased.

(4) By using the dual port RAM 4 as a font cache memory, there is no need to perform new font development for outline fonts that have already been developed and held in the dual port RAM 4.

(5) When drawing a dot pattern in page memory 1o through outline font expansion, not only memory write operations but also memory read operations are performed to fill in the inside of the outline font and perform pixel logic operations during outline font expansion. When it is necessary to create fonts for the same purpose, first expand the outline fonts in dual port RAM 4, which can be accessed faster than the page memory, create the necessary fonts, and then store them all in frame buffer memory, etc. Transferring data in advance is compared to repeatedly performing pixel logic operations to develop the outline font directly on the page memory 10 and memory read and write operations to fill in the interior after development. , the overall number of reads and writes to the relatively slow page memory 10 can be reduced. In other words, a relatively slow page memory 1 is used just to transfer the created font to the dual port RAM 4.
All you need to do is write access to 0. Thereby, the processing time until the final drawing is completed can be shortened.

(6) Dual port RA in the above effect (5)
The data transfer efficiency from M to the page memory 10 can be improved by the MAC 6, which can control block transfer of data. If such a DMAC6 is provided,
Even when the inside of the outline font is not filled or pixel logical operations are not performed when developing the outline font, the processing time until the final drawing is completed in the page memory 10 or the like can be shortened.

(7) The dual-port RAM 4, which is used as a work area such as a font cache, can be accessed by the CPU 2, DSP 3, and even DMA from different buses.
By forming C6 on the same semiconductor substrate with the dual port RAM 4, the dual port 1-1 is used for accessing the dual port RAM 4 for font development by the DSP 3, and for pixel logic operation processing for fonts.
RAM4 access, dual port RAM4 access for CPU2 and DMAC6 to transfer fonts created in dual port RAM4 to the outside.
CPU2 and DSP3 are dual ports 1-RAM 4
It is possible to speed up data processing and data transfer by using it as a work area.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, a case was explained in which data is transferred directly from the dual port RAM used as a work area for font development to the page memory for drawing. The font may be expanded and transferred to other memory to be stocked.

In the following explanation, the invention made by the present inventor is mainly applied to a page printer such as a laser beam printer, which is the background field of application, but the present invention is not limited thereto. CRT
It can be broadly applied to drawing for bitmap display systems such as displays, as well as other data processing systems. The present invention can be applied at least to conditions where a large amount of calculations must be performed at high speed.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the digital signal processing processor included in a data processing device has an architecture that allows high-speed execution of a large number of operations, so it can perform required operations such as floating point operations faster than when using a coprocessor such as an FPU. This allows devices that include a digital signal processing processor and a microprocessor to perform many operations faster than a data processing device that includes only a microprocessor or a microprocessor and a coprocessor such as an FPU. can be executed.

Furthermore, the digital signal processing processor performs a series of data processing on its own in parallel with the data processing operations of the microprocessor, using data processing algorithms in its built-in control memory according to instructions from the microprocessor, and is independent of the operations of the microprocessor. data processing can proceed. Therefore, while the digital signal processor is performing data processing such as floating point operations, the microprocessor can proceed with unrelated or other processing, without placing a large burden on the microprocessor. Furthermore, there is an effect that a large amount of calculations can be executed at high speed without restricting the operation of the microprocessor too much.

By providing dual-port RAM that is accessible by both the microprocessor and the digital signal processor via separate buses, the digital signal processor has a dedicated bus that is separate from the shared bus to which the microprocessor is coupled. via its dual port R
Dual-port RAM for outline fonts can now be utilized in the AM, which ensures complete parallel operation between the microprocessor and the digital signal processing processor, and allows digital fff signal processing processors such as outline font expansion. This has the effect of not only increasing the efficiency of data processing but also improving the operating efficiency of the entire system.

By providing a storage area in the microprocessor for information indicating the type of outline font that the microprocessor has instructed the digital signal processor to develop, the dual port RAM can be easily used as a font cache memory. become. By using the dual port RAM as a font cache memory, a new outline font is developed for the outline font that has already been developed and held in the dual port RAM, and the need for this is eliminated.

When drawing a dot pattern in the frame buffer memory or page memory through outline font expansion, not only memory write operations but also memory read operations are performed to fill in the outline font and perform pixel logic operations during outline font expansion. When it is necessary to create a font for a frame buffer memory or page memory, first expand the Audiline font in dual-port RAM, which can be accessed faster than the frame buffer memory or page memory, create the necessary font, and then write the font all at once to the frame. By transferring data to buffer memory, etc., data can be transferred directly to page memory or frame buffer memory.

Compared to the case where memory read operations and write operations are repeatedly performed to perform internal filling after expanding an infont, the processing time until the final drawing is completed can be shortened.

By providing a direct memory access controller that can control block transfer of data on a common bus that connects the microprocessor and dual-port RAM, it is possible to improve the efficiency of outsourcing on the frame buffer memory and page memory. .

A dual-port RAM used as a work area such as a font cache can be connected to a microprocessor and a digital signal processor that can be accessed via separate buses, and if necessary, a direct memory access controller to the dual-port RAM. 1-RA
By forming M on the same semiconductor substrate, dual-port RAM access for font development by a digital signal processor, dual-port RAM for filling processing of developed fonts, etc.
Dual port RAM access is used to transfer fonts created in dual port RAM to the outside by microprocessors and direct access controllers. Microprocessors and digital signal processing processors often use dual port RAM as work areas. Data processing and data transfer can be particularly accelerated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a single-chip microcomputer that is an embodiment of the present invention, FIG. 2 is a block diagram showing an example of an outline font drawing system to which the single-chip microcomputer of FIG. 1 is applied, and FIG. 3A. 3E are explanatory diagrams showing step by step an example of the operation of the outline font drawing system shown in FIG. FIG. 5B is an explanatory diagram showing another example of outline font development and transfer format. Figure 6 is a block diagram showing an example of a connection between a DSP and dual port RAM, Figure 7 is a block diagram showing another example of a connection between a DSP and dual port RAM, and Figure 8 is a dual port that can be accessed in parallel. FIG. 9 is a block diagram showing an example of a RAM; FIG. 9 is a block diagram of a dual-port RAM that utilizes a single-port RAM; FIG. 10 is a system block diagram in which the system shown in FIG. 2 is formed on a wiring board. FIGS. 12A to 12C are schematic system configuration diagrams when a plurality of DSPs are used in a multiprocessor manner. 1...Single chip micro clone computer, 2...
・CPU, 3...DSP, 4...Dual port R
AM, 5...internal bus, 6...DMAC, 7...
Peripheral circuit. 8... External bus, 9... Outline font data memory, 10... Page memory, 13... Dedicated bus, 14... Program memory, 15... Micro sequencer, 17... Register, 18 ...Arithmetic unit. Fig. 1 Fig. 2 Fig. 3A Fig. 3B Fig. 5/9 II Fig. 4A Fig. 6 ゝ゛1 Fig. 48 Fig. 5A Fig. 5B Fig. 6 ゝ゛5 Fig. 7 Fig. 10 Fig. 1. Display of incidents 1999 Patent Application No. 152718 2, Name of the invention Data processing device 3, Relationship with the case of the person making the amendment Patent applicant name (sio) Hitachi, Ltd. 4, Agent Maeda, 11 Kanda Ogawamachi-chome, Chiyoda-ku, Tokyo Building 3F March 13, 1990 (Shipped on March 20, 1990) 7. After "System block diagram," on page 44, line 5 of the amendment statement. Add "Figure 11 is a diagram of m formats of outline font data."that's all

Claims (1)

[Scope of Claims] 1. A digital signal processing processor including a microprocessor, a sequence control unit whose operation is instructed by the microprocessor, an execution unit, and a control memory in which data processing algorithms are described, on one semiconductor substrate. A data processing device comprising: 2. The data processing device according to claim 1, further comprising a dual port RAM that can be accessed by both the digital signal processor and the microprocessor via different buses. 3. A digital signal processing processor including a microprocessor, a sequence control unit whose operation is instructed by the microprocessor, an execution unit, and a control memory that describes a data processing algorithm, and this digital signal processing processor mutually. a dual-port RAM accessible via a separate bus. 4. The data processing device according to claim 2 or 3, wherein the control memory includes a data processing algorithm for developing the outline font data in the form of a dot pattern in the dual port RAM. 5. The data processing device according to claim 2, wherein a direct memory access controller capable of controlling block transfer of data is connected to the access port on the microprocessor side of the dual port RAM. 6. The data processing apparatus according to claim 4, wherein the microprocessor has a storage area for storing information indicating the type of outline font that the digital signal processor is instructed to develop.