CN112579520A - Computer architecture, system and design method for high-speed stream processing - Google Patents
Computer architecture, system and design method for high-speed stream processing Download PDFInfo
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- CN112579520A CN112579520A CN202011476873.1A CN202011476873A CN112579520A CN 112579520 A CN112579520 A CN 112579520A CN 202011476873 A CN202011476873 A CN 202011476873A CN 112579520 A CN112579520 A CN 112579520A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/82—Architectures of general purpose stored program computers data or demand driven
- G06F15/825—Dataflow computers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
A computer architecture, a system and a design method facing high-speed stream processing are provided, the computer architecture comprises a dual-port memory, a first port of the dual-port memory is connected with a CPU through a first bus, and a second port of the dual-port memory is connected with a high-speed I/O device through a second bus. The invention also provides a computer system adopting the computer architecture facing the high-speed stream processing. The design method comprises the steps of realizing high-speed data transmission between the CPU and a first port of the dual-port memory through a first bus; high-speed data transmission between a second port of the dual-port memory and the high-speed I/O equipment is realized through a second bus; and high-speed data transmission between the CPU and the high-speed I/O equipment is realized through the third bus. The invention can effectively reduce the conflict of accessing the memory through the bus, thereby improving the memory access efficiency of the system and finally realizing higher overall performance of the system.
Description
Technical Field
The invention belongs to the field of computer architecture design, and particularly relates to a high-speed stream processing-oriented computer architecture, a high-speed stream processing-oriented computer system and a high-speed stream processing-oriented computer architecture design method.
Background
Almost all computers today are designed based on von neumann architectures, which are memory-centric computer architectures from which instructions and operands executed by the computer during program execution originate, resulting in the memory easily becoming a performance bottleneck for the computer. Modern computers employ cache technology to improve the memory access efficiency of the computer. However, the premise that cache improves the access efficiency of a computer is that instructions and data meet locality characteristics, and when the instructions or data deviate from the locality characteristics, cache cannot effectively improve the access efficiency of a memory.
In high-speed stream processing such as network data packet processing, a large number of data frames arrive at a processor, and the processor only needs to process a small amount of information of a packet header. The CPU accessing the high-speed I/O device generally needs to go through 4 processes as shown in FIG. 1, and 1, the high-speed I/O device transfers data to the memory through DMA; 2. the CPU accesses the data stored in the memory; 3. the CPU modifies part of data in the memory; 4. the high speed I/O device sends the data through the I/O by DMA. In this process, both the I/O device and the CPU need to access the memory twice, and in high speed I/O device applications, the memory becomes a computer performance bottleneck.
Disclosure of Invention
The present invention is directed to a system and a method for designing a computer architecture for high-speed streaming processing, which effectively reduce the performance bottleneck of a memory, and solve the problem of low overall processing efficiency of a computer system in the prior art.
In order to achieve the purpose, the invention has the following technical scheme:
a computer architecture facing high-speed stream processing comprises a dual-port memory, wherein a first port of the dual-port memory is connected with a CPU through a first bus, and a second port of the dual-port memory is connected with a high-speed I/O device through a second bus.
As a preferred scheme of the computer architecture for high-speed stream processing according to the present invention, the CPU and the high-speed I/O device are connected by a third bus.
As a preferred embodiment of the computer architecture for high-speed stream processing according to the present invention, the first bus is an exclusive bus, and no other device is attached to the bus.
As a preferred scheme of the computer architecture for high-speed stream processing, the dual-port memory is a dual-port DRAM memory.
As a preferred embodiment of the computer architecture for high-speed stream processing according to the present invention, a plurality of high-speed I/O devices are provided, and the plurality of high-speed I/O devices are respectively connected to the second bus and the third bus.
The invention also provides a computer system which adopts the computer architecture facing the high-speed stream processing.
The invention also provides a design method of a computer architecture facing high-speed stream processing, which realizes high-speed data transmission between the CPU and the first port of the dual-port memory through the first bus; high-speed data transmission between a second port of the dual-port memory and the high-speed I/O equipment is realized through a second bus; and high-speed data transmission between the CPU and the high-speed I/O equipment is realized through the third bus.
Compared with the prior art, the invention has the following beneficial effects: the dual-port memory is respectively used for the access of the CPU and the high-speed I/O equipment, so that the access conflict between the CPU and the high-speed I/O equipment is reduced, and the access efficiency is improved. The invention solves the performance problem of accessing the memory of the high-speed I/O equipment and the CPU by increasing the access port of the memory and the redundancy of the bus.
Compared with the prior art, the computer system can effectively reduce the conflict of accessing the memory through the bus, thereby improving the memory access efficiency of the system and finally realizing higher overall performance of the system.
Drawings
FIG. 1 is a diagram of a conventional CPU accessing a high speed I/O device with arrows indicating data flow and numbers on the arrows indicating transfer order.
FIG. 2 is a schematic diagram of the architecture of the high-speed streaming oriented computer of the present invention;
in the drawings: 1-dual port memory; 2-a CPU; 3-high speed I/O devices; 4-a first bus; 5-a second bus; 6-third bus.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The invention provides a computer architecture for high-speed stream processing, which can effectively reduce the performance bottleneck of a memory and improve the overall processing efficiency of a computer system. The computer architecture provided by the embodiment of the invention solves the performance problem of accessing the memory of the high-speed I/O equipment and the CPU by means of a dual-port DRAM memory and a three-bus structure and by means of increasing memory access ports and bus redundancy. The overall performance of the system is finally improved by improving the memory access efficiency of the system.
Referring to fig. 2, the computer architecture for high-speed stream processing according to the present invention includes a dual-port memory 1, a first port of the dual-port memory 1 is connected to a CPU 2 through a first bus 4, and a second port of the dual-port memory 1 is connected to a high-speed I/O device through a second bus 5. The CPU 2 is connected with the high-speed I/O device through a third bus 6.
The first bus 4 is an exclusive bus to which no other devices are attached.
The dual port memory 1 is a dual port DRAM memory.
There are a plurality of high speed I/O devices connected to the second bus 5 and the third bus 6, respectively.
The invention also provides a computer system which adopts the computer architecture facing the high-speed stream processing.
A design method of a computer architecture facing high-speed stream processing comprises the following steps:
high-speed data transmission between the CPU 2 and the first port of the dual port memory 1 is realized through the first bus 4;
high-speed data transmission between a second port of the dual-port memory 1 and the high-speed I/O device is realized through a second bus 5;
high-speed data transmission between the CPU 2 and the high-speed I/O device is realized through the third bus 6.
The above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the technical solution of the present invention, and it should be understood by those skilled in the art that the technical solution can be modified and replaced by a plurality of simple modifications and replacements without departing from the spirit and principle of the present invention, and the modifications and replacements also fall into the protection scope covered by the claims.
Claims (7)
1. A computer architecture for high-speed stream processing, characterized by: the system comprises a dual-port memory (1), wherein a first port of the dual-port memory (1) is connected with a CPU (2) through a first bus (4), and a second port of the dual-port memory (1) is connected with a high-speed I/O device (3) through a second bus (5).
2. The high-speed stream processing-oriented computer architecture of claim 1, wherein:
the CPU (2) is connected with the high-speed I/O device (3) through a third bus (6).
3. The high-speed stream processing-oriented computer architecture of claim 1, wherein:
the first bus (4) is an exclusive bus, and other equipment is not connected to the bus.
4. The high-speed stream processing-oriented computer architecture of claim 1, wherein:
the dual-port memory (1) is a dual-port DRAM memory.
5. The high-speed stream processing-oriented computer architecture of claim 1, wherein:
the high-speed I/O devices (3) are provided with a plurality of high-speed I/O devices (3), and the high-speed I/O devices are respectively connected to the second bus (5) and the third bus (6).
6. A computer system, characterized by: a computer architecture for high-speed streaming oriented processing according to claim 1.
7. A design method of a computer architecture facing high-speed stream processing is characterized in that:
high-speed data transmission between the CPU (2) and the first port of the dual-port memory (1) is realized through a first bus (4); high-speed data transmission between a second port of the dual-port memory (1) and the high-speed I/O device (3) is realized through a second bus (5); high-speed data transmission between the CPU (2) and the high-speed I/O device (3) is realized through a third bus (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011476873.1A CN112579520A (en) | 2020-12-15 | 2020-12-15 | Computer architecture, system and design method for high-speed stream processing |
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| CN202011476873.1A CN112579520A (en) | 2020-12-15 | 2020-12-15 | Computer architecture, system and design method for high-speed stream processing |
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| CN202011476873.1A Pending CN112579520A (en) | 2020-12-15 | 2020-12-15 | Computer architecture, system and design method for high-speed stream processing |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02297594A (en) * | 1988-09-30 | 1990-12-10 | Hitachi Ltd | Data processor |
| JP2004139218A (en) * | 2002-10-16 | 2004-05-13 | Olympus Corp | Microprocessor |
| US20090003119A1 (en) * | 2007-06-27 | 2009-01-01 | Infineon Technologies Ag | Pseudo dual-port memory |
| CN103095537A (en) * | 2012-12-28 | 2013-05-08 | 武汉华中数控股份有限公司 | Numerical control device capable of concurrently controlling two-class industrial Ethernet bus slave station equipment |
| CN111045966A (en) * | 2019-11-19 | 2020-04-21 | 中国航空工业集团公司西安航空计算技术研究所 | Multi-node data interaction method based on peer-to-peer structure |
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2020
- 2020-12-15 CN CN202011476873.1A patent/CN112579520A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02297594A (en) * | 1988-09-30 | 1990-12-10 | Hitachi Ltd | Data processor |
| JP2004139218A (en) * | 2002-10-16 | 2004-05-13 | Olympus Corp | Microprocessor |
| US20090003119A1 (en) * | 2007-06-27 | 2009-01-01 | Infineon Technologies Ag | Pseudo dual-port memory |
| CN103095537A (en) * | 2012-12-28 | 2013-05-08 | 武汉华中数控股份有限公司 | Numerical control device capable of concurrently controlling two-class industrial Ethernet bus slave station equipment |
| CN111045966A (en) * | 2019-11-19 | 2020-04-21 | 中国航空工业集团公司西安航空计算技术研究所 | Multi-node data interaction method based on peer-to-peer structure |
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