CN111045966A - Multi-node data interaction method based on peer-to-peer structure - Google Patents
Multi-node data interaction method based on peer-to-peer structure Download PDFInfo
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- CN111045966A CN111045966A CN201911133739.9A CN201911133739A CN111045966A CN 111045966 A CN111045966 A CN 111045966A CN 201911133739 A CN201911133739 A CN 201911133739A CN 111045966 A CN111045966 A CN 111045966A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention discloses a multi-node data interaction method based on a peer-to-peer structure, and belongs to the technical field of high-reliability fault-tolerant computers. The method adopts a multi-node peer-to-peer structure, a high-speed serial bus mode and a dual-port storage mode, provides high-speed transmission capability between multiple processors or between a processor and an I/O interface, completes data interaction between multiple nodes in a limited task period, and establishes a fault-tolerant computer consisting of multiple processors, wherein the communication between the multiple nodes is mutually independent. Redundancy modes can be flexibly configured among a plurality of fault-tolerant computers, and a fault-tolerant computer system with high reliability, high safety and configuration is realized. The invention has the advantages that the transmission is carried out in a point-to-point peer-to-peer mode among the multiple nodes, the multiple links can be transmitted simultaneously, the bus efficiency is effectively improved, the hardware design is simplified, the processor resources are not occupied, the resources are integrated from the system perspective, and the comprehensive and universal levels of the fault-tolerant computer system are improved.
Description
Technical Field
The invention discloses a multi-node data interaction method based on a peer-to-peer structure, and belongs to the technical field of high-reliability fault-tolerant computers.
Background
In the technical field of high-reliability fault-tolerant computers, the fault-tolerant computers have higher requirements on the performance and the reliability of a processor, and the task functions of the fault-tolerant computers are more and more. New generations of fault tolerant computers tend to have multiple processor nodes performing a variety of different tasks. Multiple fault-tolerant computers can be configured into redundancy, and a 3 x 2 redundancy fault-tolerant computer system structure is realized.
Traditional fault-tolerant computers are divided into a plurality of computers according to task functions, and each computer adopts a redundancy mechanism to ensure reliability, so that the system is complex, large in volume and weight, high in price and mainly lack of flexible configuration capability. With the development of the times, the fault-tolerant computer integrates a plurality of functions into one computer, and a plurality of processor nodes are inevitably used for executing different functions. Data interaction among the multiprocessor nodes generally adopts a shared bus type architecture, data is forwarded through a main processor node, an interface module only interacts with the main processor node, and therefore the data interaction speed is low, the system time is occupied, and a large amount of time is spent on data interaction or forwarding by system software.
Disclosure of Invention
The purpose of the invention is as follows:
the invention provides a multi-node data interaction method based on a peer-to-peer structure, which solves the problem of transmission rate between multiprocessors or processors and I/O interfaces, aims to improve the operation and data transmission rate of a fault-tolerant computer, integrates resources from the system perspective, has high reliability, strong real-time performance and configurability, and improves the level of integration and universality of the fault-tolerant computer system.
The technical scheme of the invention is as follows:
a multi-node data interaction method based on a peer-to-peer structure is based on a hardware platform, processor nodes and bus interface module nodes in the hardware platform belong to the peer-to-peer structure, the nodes are transmitted in a point-to-point mode, and through a high-speed serial bus mode and a dual-port storage mode, DMA high-speed data interaction is carried out on multiple nodes without occupying processor resources. The nodes include processor nodes and processor nodes, processor nodes and bus interface module nodes, and bus interface module nodes.
Preferably, each node in the hardware platform has a different number of dual-port memories, and each dual-port memory has an independent point-to-point transmission link.
Preferably, the point-to-point transmission link is a high-speed differential serial bus, uses a high-speed serdes interface of an FPGA chip, and has 8B/10B coding and decoding capabilities.
Preferably, each processor node in the hardware platform is responsible for different operation control functions, and each processor has the capability of accessing the bus interface module and performs data communication with external equipment through the bus interface module.
Preferably, the dual-port memory of the processor node or the bus interface module node is divided into a receiving area and a sending area, and after the system software writes the sending data into the sending area, the system software can continue to execute other functions; if the hardware logic inquires that the data in the sending area of the dual-port memory is updated, the data is forwarded to the serial bus logic part; the data receiving process is opposite to the sending process, the sending process and the receiving process are physically independent, and the two ends from point to point belong to a peer-to-peer structure and can simultaneously transmit data.
Preferably, the high-speed serial bus adopts a custom protocol, and the custom protocol is divided into the following parts according to the type of transmission data: write data, write registers, read registers, and define each type of data format.
The invention has the advantages that:
the invention adopts a multi-node peer-to-peer structure, a high-speed serial bus and a dual-port memory, provides high-speed transmission capability between multiprocessors or processors and I/O interfaces, transmits in a point-to-point mode among multiple nodes, can simultaneously transmit a plurality of links, effectively improves the bus efficiency, simplifies the hardware design, does not occupy processor resources, integrates the resources from the system perspective, has high reliability, strong real-time performance and configurability, and improves the level of integration and universality of a fault-tolerant computer system.
The invention can not only improve the performance of the fault-tolerant computer, but also integrate the system resources. The fault-tolerant computers are configured into redundancy, a high-reliability configurable computer system is realized, high safety and strong real-time performance are achieved, and different requirements of different airplane management functions on redundancy configuration are met.
Description of the drawings:
FIG. 1 is a diagram of a multi-node data interaction architecture based on a peer-to-peer architecture
FIG. 2 is a diagram of a fully interconnected peer-to-peer network architecture
FIG. 3 is a high speed serial bus transmit and receive logic diagram
FIG. 4 is a schematic diagram of a point-to-point transmission link structure
FIG. 5 is a high speed serial bus custom protocol data frame format
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The hardware platform is based on a multiprocessor node, a bus interface module node and a point-to-point transmission link, the nodes at two ends of the point-to-point transmission link belong to a peer-to-peer structure, and the nodes are transmitted in a point-to-point mode without master and slave and have the capability of sending and receiving data. Through the high-speed serial bus technology and the dual-port storage technology, multiple nodes perform DMA high-speed data interaction, and processor resources are not occupied.
Referring to fig. 1, the hardware platform has 4 processor nodes respectively responsible for different operation control functions, and the 4 processors all have the capability of accessing the bus interface module node and perform data communication with external equipment through the bus interface module node. Each node has a different number of dual port memories, with an independent point-to-point transmission link for each dual port memory. Each processor node has 5 dual port memories for inter-processor, bus interface module node data interaction respectively. Each bus interface module node has 4 dual port memories for data interaction with 4 processors, respectively. In addition, the multiple processors are provided with synchronous interfaces, the multiple processors can perform high-speed data interaction and synchronous operation, and a high-reliability fault-tolerant computer system consisting of multiple processing modules is constructed.
Referring to fig. 2, the hardware platform includes 4 processor nodes and 2 bus interface module nodes, where the 2 bus interface module nodes do not require data interaction, and all other nodes have point-to-point transmission links, and there are 14 pairs of differential high-speed serial buses to form a fully interconnected peer-to-peer network structure.
Referring to fig. 3, the dual port memory of the processor CPU1 node is divided into a receive area and a transmit area, and after the system software writes transmit data into the CC _ DPRAM transmit area, the system software can continue to perform other functions. And the hardware logic inquires that the data in the CC _ DPRAM sending area is updated, forwards the data to a serial bus logic part, the serial bus logic comprises a data link layer and a physical layer, and after information such as a packet header, a packet tail, a check code and the like is added, differential signals are used for data transmission through a differential driver.
After the data from the CPU1 node is transmitted via high-speed differential serial bus, the data is automatically received by hardware logic, and the effective data is stored in the receiving area of the dual-port memory CPU1_ DPRAM of the CC bus node after the information such as packet header, packet tail and check code is removed by the data link layer and the physical layer. The CC bus node periodically reads the CPU1_ DPRAM recipient data and sends it to the CC bus via the CC bus hardware logic.
In addition, the working principle and the application mode of other nodes are the same as those of the processor CPU1 node, and are not described herein again.
Referring to fig. 4, each point-to-point transmission link is a high-speed differential serial bus, uses a high-speed serdes interface of an FPGA chip, and has 8B/10B encoding and decoding capabilities, and an encoding mode has error correction and error detection capabilities. The high-speed serial bus interface is in a full duplex mode, and transmission and reception can be performed simultaneously. The serial bus eliminates a complex application communication protocol and has extremely low overhead. The system software only needs to operate the dual-port memory, and the bus data sending and receiving operations are realized by using hardware logic.
Referring to fig. 5, the high-speed serial bus uses a custom protocol, and the protocol encapsulates data into frames, so that a receiver can correctly identify the start and end of one-time data transmission, control and error detection of the data transmission are facilitated, and the protocol function is conveniently expanded. In order to reduce transmission overhead, the protocol data frame consists of a frame head (SF), data (D) and a frame tail (EF), and CRC is checked.
The self-defined protocol is divided into the following parts according to the transmission data types: write data, write register, read register.
a) Writing data, the data format is as follows:
frame header + start address + data length word + transmission data + frame tail + check word
The protocol is a full duplex protocol, and the sending interface and the receiving interface of each path are fixed, so that the sending end and the receiving end are determined. The transmitting end needs to fill data according to a frame format and then transmits the data to the serial bus through the transmitting interface. And the receiving end detects that data exists, and stores the received data into the local dual-port memory according to the starting address and the data length word in the frame format.
b) Writing the register, and the data format is as follows:
frame header + start address + data length word + attribute (write register) + register value + frame tail + check word
And writing the register value in the frame format to a specific position of the opposite dual-port memory according to the starting address and the data length word.
c) Reading the register, and the data format is as follows:
frame header + start address + data length word + attribute (read register) + frame tail + check word
The type data format is mainly used for the processor node to obtain the register information of the bus interface node, plays a role of informing the other side to send the register information, and the bus interface node sends the register information to the processor node according to the data format of writing the register.
Claims (6)
1. A multi-node data interaction method based on a peer-to-peer structure is characterized in that: the method is based on a hardware platform, processor nodes and bus interface module nodes in the hardware platform belong to a peer-to-peer structure, the nodes are transmitted in a point-to-point mode, and multiple nodes carry out DMA high-speed data interaction through a high-speed serial bus mode and a dual-port storage mode.
2. The peer-to-peer architecture based multi-node data interaction method as claimed in claim 1, wherein: each node in the hardware platform has a different number of dual-port memories, and each dual-port memory has an independent point-to-point transmission link.
3. The peer-to-peer structure based multi-node data interaction method as claimed in claim 2, wherein: the point-to-point transmission link is a high-speed differential serial bus, uses a high-speed serdes interface of an FPGA chip, and has 8B/10B coding and decoding capabilities.
4. The peer-to-peer structure based multi-node data interaction method as claimed in claim 2, wherein: each processor node in the hardware platform is respectively responsible for different operation control functions, and each processor has the capability of accessing the bus interface module and carries out data communication with external equipment through the bus interface module.
5. A peer-to-peer based multi-node data interaction method as claimed in claim 1 or 2, wherein: the dual-port memory of the processor node or the bus interface module node is divided into a receiving area and a sending area, and after the system software writes the sending data into the sending area, the system software can continuously execute other functions; if the hardware logic inquires that the data in the sending area of the dual-port memory is updated, the data is forwarded to the serial bus logic part; the data receiving process is opposite to the sending process, the sending process and the receiving process are physically independent, and the two ends from point to point belong to a peer-to-peer structure and can simultaneously transmit data.
6. The peer-to-peer architecture based multi-node data interaction method as claimed in claim 1, wherein: the high-speed serial bus adopts a custom protocol which is divided into the following parts according to the transmission data types: write data, write registers, read registers, and define each type of data format.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112579520A (en) * | 2020-12-15 | 2021-03-30 | 西安邮电大学 | Computer architecture, system and design method for high-speed stream processing |
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| CN104539503A (en) * | 2014-12-11 | 2015-04-22 | 中国航空工业集团公司第六三一研究所 | Method for achieving redundancy channel data cross transmission based on 1394 bus autonomous forwarding |
| CN108616435A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Double redundant system data transmission methods based on high-speed serial bus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104461793A (en) * | 2014-12-05 | 2015-03-25 | 中国航空工业集团公司第六三一研究所 | High-reliability multinode fault-tolerant computer system and synchronization method |
| CN104539503A (en) * | 2014-12-11 | 2015-04-22 | 中国航空工业集团公司第六三一研究所 | Method for achieving redundancy channel data cross transmission based on 1394 bus autonomous forwarding |
| CN108616435A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Double redundant system data transmission methods based on high-speed serial bus |
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