KR900005303A - Data processing unit - Google Patents

Abstract

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Description

Data processing unit

Since this is an open matter, no full text was included.

1 is a block diagram showing a single chip microcomputer as an embodiment of the present invention;

2 is a block diagram showing an example of an outline font drawing system to which the single-chip microcomputer of FIG. 1 is applied;

4 is an explanatory diagram showing an example of the expansion and transmission format of an outline font.

Claims (12)

A microprocessor, a first bus to which the microprocessor is coupled, storage means coupled to the first bus and maintaining a data processing order, to data coupled to the storage means and transmitted via the first bus A digital signal processing processor having execution means for executing processing according to the order held in said storage means, a second bus coupled to said digital signal processor and a first port coupled to said first bus and said And a dual port memory having a second port coupled to a second bus and formed on a semiconductor substrate. A data processing apparatus according to claim 1, wherein outline font data in a memory for holding outline font data is transmitted to said first bus. A microprocessor, a first bus to which the microprocessor is coupled, memory means coupled to the first bus and maintaining a data processing order, and data coupled to the memory means and transmitted via the first bus. A digital signal processing processor having execution means for executing processing in the order held in the storage means, a second bus coupled to the digital signal processing processor, a first port coupled to the first bus, and the second bus; And a dual-port memory having a second port coupled to a bus of the. 4. A data processing apparatus according to claim 3, wherein outline font data in a memory holding outline font data is transmitted to said first bus. And a digital signal processing processor having a microprocessor and a sequence control unit in which operation is instructed by the microprocessor, an execution unit, and a controller storage unit in which a data processing algorithm is described. 6. A data processing apparatus according to claim 5, further comprising a dual-port RAM accessible via different buses on both the digital signal processing processor and the microprocessor. A digital signal processing processor having a microprocessor, a sequence control unit in which an operation is instructed by the microprocessor, an execution unit, and a controller storage unit in which a data processing algorithm is described, and a bus different from each of the digital signal processing processor and the microprocessor. Data processing unit including dual-port RAM accessible via. 8. A data processing apparatus according to claim 7, wherein said control storage means includes a data processing algorithm for deploying outline font data to said dual port RAM in the form of a dot pattern. The data processing apparatus according to claim 8, further comprising a direct memory access controller capable of controlling block transfer of data coupled to an access port on the microprocessor side in the dual port RAM. 7. A data processing apparatus according to claim 6, wherein said control storage means comprises a data processing algorithm for developing the outline font data in a dual port RAM in the form of a tote pattern. 11. A data processing apparatus according to claim 10, further comprising a direct memory access controller capable of controlling block transfer coupled to an access port on the microprocessor side of said dual port RAM. The data processing apparatus according to claim 11, wherein the microprocessor has an area for holding information indicating the type of the outline font instructing the digital signal processing processor to expand. ※ Note: The disclosure is based on the initial application.