KR970056649A - National data processing device using shared memory in all electronic exchange - Google Patents

National data processing device using shared memory in all electronic exchange Download PDF

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Publication number
KR970056649A
KR970056649A KR1019950069192A KR19950069192A KR970056649A KR 970056649 A KR970056649 A KR 970056649A KR 1019950069192 A KR1019950069192 A KR 1019950069192A KR 19950069192 A KR19950069192 A KR 19950069192A KR 970056649 A KR970056649 A KR 970056649A
Authority
KR
South Korea
Prior art keywords
shared memory
memory
processor
data processing
processing device
Prior art date
Application number
KR1019950069192A
Other languages
Korean (ko)
Other versions
KR0177970B1 (en
Inventor
정수진
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019950069192A priority Critical patent/KR0177970B1/en
Publication of KR970056649A publication Critical patent/KR970056649A/en
Application granted granted Critical
Publication of KR0177970B1 publication Critical patent/KR0177970B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M2201/00—Electronic components, circuits, software, systems or apparatus used in telephone systems
    • H04M2201/36—Memories

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

본 발명은 전전자 교환기에 있어서 공유 메모리를 이용한 국데이타 처리 장치에 관한 것으로서, 본 발명의 장치는 국데이타를 저장하기 위한 공유 메모리(10); 로컬 메모리만을 구비하고 있으며, 국 데이타를 생성하여 상기 공유 메모리(10)에 저장하는 제1프로세서(20); 및 로컬 메모리만을 구비하고 있으며, 상기 공유 메모리(10)에 저장된 국데이타를 읽어와 처리하는 다수개의 제2프로세서(30, 40, 50, 60)로 구성되어 있어, 각 프로세서내의 국데이타를 저장하기 위한 수단을 없애고 별도로 하나의 공유 메모리 수단을 두어 국데이타를 상기 공유 메모리에서 관리함으로써, 상기 프로세서의 불필요한 메모리 용량을 감소시킬 뿐만 아니라 프로세서의 부하 자체도 감소시킨다는 데 그 효과가 있다.The present invention relates to a national data processing apparatus using a shared memory in an electronic switching system, the apparatus of the present invention comprises: a shared memory (10) for storing national data; A first processor (20) having only a local memory and generating station data in the shared memory (10); And a plurality of second processors (30, 40, 50, and 60) for reading and processing the station data stored in the shared memory (10), having only a local memory, and storing the station data in each processor. By eliminating the means for managing the state data in the shared memory by having a separate shared memory means, there is an effect that not only reduces the unnecessary memory capacity of the processor, but also reduces the load of the processor itself.

Description

전전자 교환기에 있어서 공유 메모리를 이용한 국데이타 처리 장치National data processing device using shared memory in all electronic exchange

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 전전자 교환기의 국데이타 처리 장치에 대한 구성도.1 is a block diagram of a state data processing apparatus of a general electronic exchanger.

제2도는 본 발명에 따른 전전자 교환기에 있어서 공유 메모리를 이용한 국데이타 처리 장치에 대한 구성도.2 is a block diagram of a national data processing apparatus using a shared memory in the electronic switch according to the present invention.

제3도는 본 발명에 따른 장치를 적용하기 위해 데이타 화일을 생성하는 과정을 도시한 흐름도이다.3 is a flowchart illustrating a process of generating a data file for applying the apparatus according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 공유 메모리 20 : 제1 프로세서10: shared memory 20: first processor

30, 40, 50, 60 : 제2 프로세서 20a, 30a, 40a, 50a, 60a : 로컬 메모리30, 40, 50, 60: second processor 20a, 30a, 40a, 50a, 60a: local memory

Claims (1)

국데이타를 저장하기 위한 공유 메모리(10)와; 로컬 메모리만을 구비하고 있으며, 국 데이타를 생성하여 상기 공유 메모리(10)에 저장하는 제1프로세서(20); 및 로컬 메모리만을 구비하고 있으며, 상기 공유 메모리(10)에 저장된 국데이타를 읽어와 처리하는 다수개의 제2프로세서(30, 40, 50, 60)로 구성되어 있는 것을 특징으로 하는 전자 교환기에 있어서 공유 메모리를 이용한 국데이타 처리 장치.A shared memory (10) for storing station data; A first processor (20) having only a local memory and generating station data in the shared memory (10); And a second memory (30, 40, 50, 60) having only a local memory and configured to read and process the station data stored in the shared memory (10). Station data processing device using memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069192A 1995-12-30 1995-12-30 Data processor using shared memory in digital exchange KR0177970B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069192A KR0177970B1 (en) 1995-12-30 1995-12-30 Data processor using shared memory in digital exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069192A KR0177970B1 (en) 1995-12-30 1995-12-30 Data processor using shared memory in digital exchange

Publications (2)

Publication Number Publication Date
KR970056649A true KR970056649A (en) 1997-07-31
KR0177970B1 KR0177970B1 (en) 1999-05-15

Family

ID=19448340

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950069192A KR0177970B1 (en) 1995-12-30 1995-12-30 Data processor using shared memory in digital exchange

Country Status (1)

Country Link
KR (1) KR0177970B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010009944A (en) * 1999-07-14 2001-02-05 윤종용 Method for owning configuration information of board jointly in mobile telecommunication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010009944A (en) * 1999-07-14 2001-02-05 윤종용 Method for owning configuration information of board jointly in mobile telecommunication system

Also Published As

Publication number Publication date
KR0177970B1 (en) 1999-05-15

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