KR940015843A - How to Support Data Transfer Between Processor Boards in a Multiprocessor System - Google Patents

How to Support Data Transfer Between Processor Boards in a Multiprocessor System Download PDF

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Publication number
KR940015843A
KR940015843A KR1019920025008A KR920025008A KR940015843A KR 940015843 A KR940015843 A KR 940015843A KR 1019920025008 A KR1019920025008 A KR 1019920025008A KR 920025008 A KR920025008 A KR 920025008A KR 940015843 A KR940015843 A KR 940015843A
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KR
South Korea
Prior art keywords
processor
board
processor board
data
address
Prior art date
Application number
KR1019920025008A
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Korean (ko)
Other versions
KR950005795B1 (en
Inventor
기안도
한종석
윤석한
윤용호
Original Assignee
양승택
재단법인 한국전자통신연구소
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Priority to KR1019920025008A priority Critical patent/KR950005795B1/en
Publication of KR940015843A publication Critical patent/KR940015843A/en
Application granted granted Critical
Publication of KR950005795B1 publication Critical patent/KR950005795B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

본 발명은 동기형 버스를 채용한 다중처리기 시스템에서 프로세서 보드들간의 데이타 전송을 지원하는 방법에 관한 것으로, 하나의 프로세서 보드가 필요로 하는 데이타가 어떤 메모리 보드에 있지만 실제로 유효한 데이타가 다른 하나의 프로세서 보드에 있어면 메모리 보드에 대한 참조없이 두 프로세서 보드간에 직접 데이타의 송수신이 가능하게 한다.The present invention relates to a method for supporting data transfer between processor boards in a multiprocessor system employing a synchronous bus. On board, this allows direct transfer of data between two processor boards without a reference to the memory board.

Description

다중 프로세서 시스템에서 프로세서 보드 사이의 데이타 전송을 지원하는 방법How to Support Data Transfer Between Processor Boards in a Multiprocessor System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명을 나타낸 타이밍도로서 프로세서 보드 사이의 데이타 전송동작의 타이밍도.4 is a timing diagram showing the present invention and a timing diagram of a data transfer operation between processor boards.

Claims (1)

동기형 시스템 버스(3)에 연결된 적어도 2개 이상의 프로세서 보드를 갖는 다중처리기 시스템에서 하나의 프로세서 보드로 부터 다른 하나의 프로세서 보드로 데이타를 전송하는 방법에 있어서, 소정의 데이타를 원하는 제1프로세서 보드가 읽기 어드레스를 구동하는 단계와, 상기 읽기 어드레스와 관련된 제2프로세서 보드가 읽기 응답 어드레스 신호를 상기 제1프로세서 보드로 제공하고 상기 읽기 어드레스와 관련된 제1메모리 보드의 버스동작을 중지시키는 단계와, 상기 제2프로세서 보드는 상기 읽기 어드레스와 관련된 데이타를 준비하고 상기 시스템버스(3)상에 쓰기 어드레스를 구동하기 위한 중재를 수행한 후 상기 쓰기 어드레스를 구동하는 단계와, 상기 쓰기 어드레스와 관련된 제2메모리 보드로 부터 쓰기 어드레스 응답신호가 구동되면 상기 제2프로세서 보드는 상기 제2메모리 보드의 버스동작을 중지시켜 데이타가 상기 제2프로세서 보드로 부터 상기 제1프로세서 보드로 직접 전달하게 하는 단계와, 상기 데이타를 받아들인 상기 제1프로세서 보드가 데이타 응답신호를 구동하여 데이타 전송동작을 완료하는 단계를 포함하는 것을 특징으로 하는 다중 프로세서 시스템에서 프로세서 보드 사이의 데이타 전송을 지원하는 방법.A method for transferring data from one processor board to another in a multiprocessor system having at least two processor boards connected to a synchronous system bus (3), comprising: a first processor board for which desired data is desired; Driving a read address, providing a read response address signal to the first processor board by the second processor board associated with the read address and stopping a bus operation of the first memory board associated with the read address; Driving the write address after preparing the data related to the read address and performing arbitration to drive the write address on the system bus 3, and the second processor board related to the write address. When the write address response signal is driven from the memory board, The second processor board stops bus operation of the second memory board to transfer data directly from the second processor board to the first processor board, and the first processor board receiving the data A method of supporting data transfer between processor boards in a multiprocessor system comprising driving a response signal to complete a data transfer operation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920025008A 1992-12-22 1992-12-22 Method helping data to be transmitted between process boards in multi processor system KR950005795B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920025008A KR950005795B1 (en) 1992-12-22 1992-12-22 Method helping data to be transmitted between process boards in multi processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920025008A KR950005795B1 (en) 1992-12-22 1992-12-22 Method helping data to be transmitted between process boards in multi processor system

Publications (2)

Publication Number Publication Date
KR940015843A true KR940015843A (en) 1994-07-21
KR950005795B1 KR950005795B1 (en) 1995-05-31

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KR1019920025008A KR950005795B1 (en) 1992-12-22 1992-12-22 Method helping data to be transmitted between process boards in multi processor system

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390579B1 (en) * 2000-11-08 2003-07-07 주식회사 하이닉스반도체 Device and method for communicating multi between higher board and lower board
KR101291783B1 (en) * 2012-05-31 2013-07-31 에이스웨이브텍(주) Test apparatus for synchro signal to digital converter

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101797929B1 (en) * 2015-08-26 2017-11-15 서경대학교 산학협력단 Assigning processes to cores in many-core platform and communication method between core processes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390579B1 (en) * 2000-11-08 2003-07-07 주식회사 하이닉스반도체 Device and method for communicating multi between higher board and lower board
KR101291783B1 (en) * 2012-05-31 2013-07-31 에이스웨이브텍(주) Test apparatus for synchro signal to digital converter

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Publication number Publication date
KR950005795B1 (en) 1995-05-31

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