KR101797929B1 - Assigning processes to cores in many-core platform and communication method between core processes - Google Patents

Abstract

The present invention relates to a method for allocating a process to a core in a ManiCore platform and a method for communication between core processes.
According to the present invention, in a manifold platform including a plurality of cores, a communication bus connecting each of the cores, a data bus connecting the cores, and storing data stored in a register provided in the first core directly, A core bus switch for switching the communication bus and the user dynamic network, and a user dynamic network controller for switching the user dynamic network, And a demultiplexing buffer for storing data received through a network and a cache memory.

Description

TECHNICAL FIELD [0001] The present invention relates to a method for assigning a process to a core in a ManiCore platform, and a method for communicating between the core process and a core process.

The present invention relates to a method for allocating a process to a core in a ManiCore platform and a method for communicating between core processes. More particularly, the present invention relates to a communication method and a process allocation between cores when processing a process on a multi- A method for allocating a process to a core in an optimizing < RTI ID = 0.0 > ManiCore < / RTI >

The development of the current processor is moving toward the optimization and optimization of a single processor into multiple cores rather than improving the technical performance of a single core, and a multi-core CPU (Central Processing Unit) is also installed in a small portable device.

In response to this trend, processors for high-performance computing consist of dozens of cores, and the name for these processors is called the ManiCORE processor or ManiCore platform.

As the number of cores in one processor increases and this becomes common, interest and importance of parallel processing method that efficiently use multiple cores is increased.

In order to maximize the performance of high-performance computing, the process must be efficiently distributed to multiple cores, and communications between the cores must also be performed in a manner that does not delay processing of the cores.

Conventionally, the conventional parallel processing method has a disadvantage that it can not completely bring out the maximum computing performance of the process. In view of the current trend, such a disadvantage will become more prominent as time passes. Therefore, a new parallel processing method capable of solving the above problems is needed.

Korean Patent Publication No. 10-2012-0066189 (2012.06.22. Open)

With the development of the Manicore platform, parallel programming problems are increasing day by day. This is because there is a difference between a hardware parallel structure and a software parallel structure. SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method for efficiently assigning cores in a manifold platform and creating a direct communication path between cores, And to provide the above objects.

The above object of the present invention is also achieved by a manifold platform in which a plurality of cores included in a first core and a second core are arranged in the horizontal and vertical directions and the plurality of cores are interconnected by a communication bus structure in a mesh form, A user dynamic network connecting the cores and directly transmitting and receiving data stored in the registers provided in the first core directly to the registers provided in the second core and a shared memory accessible to each core, Each core includes a core processor, a communication bus, a core bus switch for switching the user dynamic network, and a cache memory. The core processor stores data received through the user dynamic network, A plurality of demultiplexing queues, and an order of data stored in the demultiplexing queue In that it comprises a buffer for demultiplexing it can be achieved by a manifold core platform as claimed.

It is a further object of the present invention to provide a method and apparatus for managing a plurality of cores in a manifold platform that includes a first core and a second core arranged in the horizontal and vertical directions, Wherein the first core and the second core each have a plurality of demultiplexing queues for storing data and the data stored in any one demultiplexing queue selected in the first core is transmitted to a user dynamic network And directly transmitting to any one of the demultiplexing queues selected in the second core using the method of the present invention.

According to an aspect of the present invention, there is provided an apparatus for inter-core communication of a plurality of cores, comprising: a communication bus configured in a mesh format between cores; a demultiplexer A demux buffer, and a demux queue coupled to the demultiplexing buffer.

The communication bus can transmit communication information between the cores in a mesh-type physical network in which all the cores of the ManiCore platform are connected in a two-dimensional square.

The communication information between the cores may include data having one or a plurality of core word sizes, and data to be transmitted to a process performed in the core is transmitted to a process performed in another core. The core word consists of a word size according to the architecture of the core constituting the ManiC platform.

The demultiplexing buffer is individually configured in each core of the manifold platform. The demultiplexing output unit is connected to a plurality of demultiplexing queues, so that the communication information received from the other core can be transmitted to the demultiplexing queue .

The demultiplexing queue is a special register connected to the demultiplexing buffer. The core receiving the communication information between the cores can recognize data contained in the communication information by reading a plurality of special registers to which the demultiplexing cues are mapped.

The direct communication method between the cores is called a user dynamic network in the present invention. Basically, communication between cores is performed for system operation. However, the method for managing parallel communication among multiple cores can be further improved.

According to the method for allocating a process to a core and the method for communicating between core processes in a ManiCore platform according to the present invention, a process is efficiently allocated to a core in a ManiCore platform, thereby effectively performing parallel processing in a real- Can be utilized. In addition, data communication between processes running on individual cores of a Manicenter platform can be handled within a short response time.

1 is a conceptual view showing a mesh structure of a 4x4 manifold platform according to the present invention;
2 is a conceptual diagram showing the structure of each core constituting a manifold platform of a mesh structure according to the present invention;
3 is a configuration diagram of a core bus switch and a core processor according to an embodiment of the present invention;
4 is a structural view of a system stack;
5 is a conceptual diagram illustrating a method of allocating threads in the manifold platform shown in FIG.
Figure 6 is an exemplary diagram illustrating a method of sharing memory in a ManiCore platform;
7 is a conceptual diagram illustrating a dynamic network between core processes over a core bus;
Figure 8 is an example of a communication using a shared memory and a user dynamic network between applications running on separate cores with a process core allocated on a manifold platform.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It is to be understood that the present invention is not intended to be limited to the specific embodiments but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

The inter-core communication bus according to the present invention is a mesh-type physical network in which all cores of the ManiCore platform are connected in a two-dimensional square manner, and can transmit communication information between the cores.

The communication information between the cores according to the present invention may include data to be transmitted to a process in which a process performed in the core is performed in another core, with data having one or a plurality of core word sizes. The core word is designed to have a word size according to the architecture of the core that constitutes the Manicure platform.

The demultiplexing buffer according to the present invention is individually configured in each core of the manifold platform. The demultiplexing output unit is connected to a plurality of demultiplexing queues, and the communication information received from the other core is transmitted to a demultiplexing queue . The demultiplexing queue is a special register connected to the demultiplexing buffer. The core receiving the communication information between the cores can recognize data contained in the communication information by reading a plurality of special registers to which the demultiplexing cues are mapped.

The ManiCore platform is a system that can provide a parallel processing environment with multiple cores of the same type. The ManiCore platform has cores capable of handling individual processes connected through a physical communications bus, and each core can transfer data to other cores. 1 is a conceptual view showing a mesh structure of a 4x4 manifold platform according to the present invention. Each core can communicate between cores using a communication bus. Core 0 is a core that performs hypervisor and supervisor tasks to perform tasks related to the operation of the system. Core 0 to core 15 are assigned tasks via a communication bus from core 0.

In the ManiCore platform, a communication bus that provides data interworking between cores is implemented as a user dynamic network, which takes precedence over a shared memory implemented on the ManiClient platform. Each core can independently process a process such as information processing.

The user dynamic network is optimized for point-to-point data communication between cores requiring minimal latency. Since the user dynamic network is based on a hardware communication bus configured for this purpose, when data is moved from one core to another core, a method of directly connecting from a register to a register without going through a cache is adopted. The performance is improved. Core processors are able to communicate directly through the user dynamic network and are particularly useful for parallel programming.

2 is a conceptual diagram showing the structure of each core constituting the manifold platform of the mesh structure according to the present invention. The core 0 is configured to include a core bus switch, a core processor, and a cache memory that connect a communication bus between the cores. Generally, information transmitted through a core bus switch is stored in a cache memory. However, in the present invention, communication is performed between core processors in real time using a user dynamic network.

3 is a configuration diagram of a core bus switch and a core processor according to an embodiment of the present invention. Specifically, the core bus switch and the core 0 processor are shown in detail. The demultiplexing queue stores the information transmitted through the user dynamic network. The core receiving the communication information between the cores accesses the demultiplexing queue through the register in which the address of the demultiplexing queue is recorded, Data can be recognized. Each core on a two-dimensional mesh structure creates a number of queues to receive information conveyed to the user's dynamic network, which is referred to as a demultiplexing queue, and the address for each queue is written to a designated register. Software running on the core's processor can access the demultiplexed queue via the address written to the register.

The information transmitted between the core and the core in the user dynamic network necessarily has a specific identification value. The identification value is used to determine which demux queue the information will be stored in when the core receives the information, and is removed after the information is stored in the queue. Therefore, when the software accesses the demultiplexing queue through the register, the information including the corresponding identification value is removed.

When several pieces of information are stored in one demultiplexing queue, in order to prevent the information that is stored first in the queue from being used by the software so that the arrived information can not be accessed while being stored in the queue, And generates a multiplexing buffer. The size of the demultiplexing buffer differs depending on the implementation, and instead of being stored in the demultiplexing queue in the order in which the information arrives at the core, the demultiplexing buffer can be used to change the order of the information stored in the queue.

There is a hypervisor layer that is a system stack that controls the hardware configuration to control the cores of the Manicenter platform. 4 is a structural view of the system stack. The hypervisor abstracts and manages all the hardware of the system as well as the Manny core platform. There is a supervisor layer that provides input / output devices for applications on the hypervisor and libraries that control the system.

When assigning threads to applications on the ManiCore platform, it is efficient to allocate threads to the core as close to the main processor as possible. In the main processor, when a new thread is created, the main processor allocates a thread to the core located close to core 0 to reduce the burden on the allocated core. 5 is a conceptual diagram illustrating a method of allocating threads in the manifold platform shown in FIG. It assigns threads to core 1, core 4, and core 5 close to core 0 to share work. The cores share information through the shared memory implemented on the ManiClient platform.

On a ManiCore platform, when an application uses two or more cores, the cores share information through shared memory implemented on the ManiClient platform. 6 is an exemplary diagram illustrating a method of sharing memory in the ManiCore platform. Core 0 shares memory with core 1 through shared memory, while core 2 shares memory with core 3. The sharing method can create shared memory between two or more applications assigned to different cores by a user, although the system can automatically create a share through thread allocation in one application. All the shared memory information is transferred through the communication bus between the cores.

In the ManiCore platform, we have specified a path to perform user dynamic networking on the core bus for direct communication between cores. This pathway allows immediate exchange of information between core processes directly without passing through shared memory or cache memory. 7 is a conceptual diagram illustrating a dynamic network between core processes over a core bus. In FIG. 7, core 0 transmits information to core 1, core 4, and core 5 via the user dynamic network. Core 1, core 4, and core 5 process the received information, . The received information between the cores is stored in the space of the demultiplexed cue, and the cue is performed in the FIFO manner. With user dynamic network, it is possible for users to transmit urgent data efficiently and quickly in system or application, effectively performing parallel programming.

FIG. 8 is a diagram illustrating a communication example in which a process core is allocated in a ManiCore platform, and a shared memory and a user dynamic network are used between applications that are run on an individual core, according to an embodiment of the present invention. Application 0 drives the main process on core 0. The main process allocates threads 1, 2, 3, and 4 to each core 1, 2, 3, and 4 to generate one thread. In this way, application 0 is driven by 5 cores in total, and applications 1, 2, 3 and 4 are individually driven in core 5, 6, 7 and 8, respectively. Application 1 shares the memory using shared memory with Core 1 allocated to Thread 1 of Application 1 through shared memory. In addition, applications 2, 3, and 4 share memory with threads 2, 3, and 4 of application 0 in the same manner, and parallel programming is possible. At the same time, applications 1, 2, 3, and 4 can exchange urgent data through the main process of application 0 and the user dynamic network. The information to be processed here is given priority over the shared memory. As described above, the present invention allows a user to freely perform real-time processing and efficiently utilize limited memory resources.

In the present invention, a plurality of cores including a first core and a second core are arranged in the horizontal and vertical directions, and communication is performed between the core processes in the manifold platform connecting the plurality of cores in a mesh- Wherein the first core and the second core each have a plurality of demultiplexing queues for storing data and the data stored in any one demultiplexing queue selected in the first core is transmitted to the second core The first core is provided with a demultiplexing buffer and the data stored in the first core is transmitted to the selected core in the first core before being transmitted to the second core, And extracting data to be transmitted to the second core from a plurality of data stored in the multiplexing queue The communication method between the core process is provided that.

In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present disclosure rather unclear.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In addition, the components shown in the embodiments of the present invention are shown independently to represent different characteristic functions, which does not mean that each component is composed of separate hardware or software constituent units. That is, each constituent unit is included in each constituent unit for convenience of explanation, and at least two constituent units of the constituent units may be combined to form one constituent unit, or one constituent unit may be divided into a plurality of constituent units to perform a function. The integrated embodiments and separate embodiments of the components are also included within the scope of the present invention, unless they depart from the essence of the present invention.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Claims (5)

delete A manifold platform for connecting a plurality of cores including a first core and a second core in a transverse and longitudinal direction and interconnecting the plurality of cores with a communication bus structure in a mesh form,
A user dynamic network that connects between the cores constituting the plurality of cores and transmits and receives data stored in the registers provided in the first cores directly to a register provided in the second cores,
Each of the cores constituting the plurality of cores includes an accessable shared memory,
In each of the cores constituting the plurality of cores
A core processor,
A core bus switch for switching the communication bus and the user dynamic network,
And a cache memory,
The core processor
A plurality of demultiplexing queues of FIFO type for storing data to be transmitted through the user dynamic network,
And a demultiplexing buffer for converting the order of the data stored in the demultiplexing queue,
Wherein the core processor further comprises a register for storing addresses of the plurality of demultiplexing queues.
3. The method of claim 2,
Wherein the data received through the user dynamic network includes an identification value for determining which demultiplexing queue is to be stored among a plurality of demultiplexing queues and the identification value is removed after the data is stored. .
delete A method for communicating between core processes in a ManiCore platform, wherein a plurality of cores including a first core and a second core are arranged in the transverse and longitudinal directions and interconnecting the plurality of cores in a mesh communication bus structure ,
Wherein the first core and the second core each have a plurality of demultiplexing queues for storing data and the data stored in any one demultiplexing queue selected from the first core is transmitted to the second core Multiplexing queues selected from among the plurality of demultiplexing queues,
Wherein the first core is provided with a demultiplexing buffer and the data stored in the first core is transmitted to the second core among a plurality of data stored in the demultiplexing queue selected in the first core Further comprising the step of fetching data that is desired to be transmitted.

Images