KR970071310A - Local bus control device - Google Patents

Local bus control device Download PDF

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Publication number
KR970071310A
KR970071310A KR1019960012934A KR19960012934A KR970071310A KR 970071310 A KR970071310 A KR 970071310A KR 1019960012934 A KR1019960012934 A KR 1019960012934A KR 19960012934 A KR19960012934 A KR 19960012934A KR 970071310 A KR970071310 A KR 970071310A
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KR
South Korea
Prior art keywords
controlling
signal processor
digital signal
slave
bus
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Application number
KR1019960012934A
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Korean (ko)
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KR100362061B1 (en
Inventor
김재훈
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960012934A priority Critical patent/KR100362061B1/en
Publication of KR970071310A publication Critical patent/KR970071310A/en
Application granted granted Critical
Publication of KR100362061B1 publication Critical patent/KR100362061B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0044—Versatile modular eurobus [VME]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 로칼 버스 제어 장치에 관한 것으로서, 특히 VME(Versa Module Euro Card)버스를 이용하는 시스템에서 병렬로 여러장의 보드를 동시에 사용할 때 디지탈 신호 프로세서가 VME 버스와는 독립적으로 동작할 수 있도록 하는 제어 장치에 관한 것이다.[0001] The present invention relates to a local bus control apparatus, and more particularly, to a system and method for controlling a local bus controller, which enables a digital signal processor to operate independently of a VME bus when a plurality of boards are used in parallel in a system using a Versa Module Euro Card (VME) .

본 발명의 목적을 위하여 디지탈 신호를 처리하는 디지탈 신호 처리기(DSP)가 마스터-슬레이브 구조인 VME 버스를 제어하는 장치에 있어서, VME 버스를 제어하는 VME 버스 제어부, 디지탈 신호 처리기가 마스터로 동작할 때 마스터 동작을 제어하여 VME 버스를 엑세스하게 하는 마스터 제어부, 디지탈 신호 처리기가 슬레이브로 동작할 때 슬레이브 동작을 제어하는 슬레이브 제어부, 디지탈 신호 처리기와 VME 버스 제어부의 로칼 버스 사용에 대한 요청 및 승인을 제어하는 로칼 버스 조정부를 포함하는 것을 특징으로 한다.In order to accomplish the object of the present invention, there is provided an apparatus for controlling a VME bus in which a digital signal processor (DSP) for processing digital signals is a master-slave structure, comprising: a VME bus controller for controlling a VME bus; A master control unit for controlling the master operation to access the VME bus, a slave control unit for controlling the slave operation when the digital signal processor operates as a slave, a digital signal processor and a VME bus control unit for controlling requests and approvals for the use of the local bus And a local bus adjustment unit.

본 발명에 의하면, 디지탈 신호 처리기가 VME 버스와 독립적으로 동작하여 속도와 호환성을 향상시킬 수 있다.According to the present invention, the digital signal processor can operate independently of the VME bus to improve speed and compatibility.

Description

로칼 버스 제어 장치Local bus control device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제4도는 본 발명에 의한 로칼 버스 제어 장치의 구성을 보이는 블럭도이다.FIG. 4 is a block diagram showing a configuration of a local bus control apparatus according to the present invention.

Claims (2)

디지탈 신호를 처리하는 디지탈 신호 처리기(DSP)가 마스터-슬레이브 구조인 VME버스를 제어하는 장치에 있어서, VME버스를 제어하는 VME버스 제어부; 상기 디지탈 신호 처리기가 마스터로 동작할 때 마스터 동작을 제어하여 상기 VME 버스를 엑세스하게 하는 마스터 제어부; 상기 디지탈 신호 처리기가 슬레이브로 동작할 때 슬레이브 동작을 제어하는 슬레이브 제어부; 상기 디지탈 신호 처리기가 상기 VME버스 제어부의 로칼 버스 사용에 대한 요청 및 승인을 제어하는 로칼 버스 조정부를 포함하는 것을 특징으로 하는 로칼 버스 제어 장치.An apparatus for controlling a VME bus in which a digital signal processor (DSP) for processing digital signals is a master-slave structure, comprising: a VME bus control unit for controlling a VME bus; A master controller for controlling the master operation to access the VME bus when the digital signal processor operates as a master; A slave controller for controlling a slave operation when the digital signal processor operates as a slave; Wherein the digital signal processor includes a local bus arbitration unit for controlling requests and acknowledgments for use of the local bus of the VME bus control unit. 제1항에 있어서, 상기 마스터 제어부 및 상기 슬레이브 제어부에서의 각각의 제어에 따라 상기 디지탈 신호 처리기 내부의 메모리 및 로칼 메모리의 선택 정보를 해독하는 해독부를 부가로 구비함을 특징으로 하는 로칼 버스 제어 장치.2. The local bus control device according to claim 1, further comprising a decoding unit for decoding selection information of a memory and a local memory in the digital signal processor according to the respective controls in the master control unit and the slave control unit, . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960012934A 1996-04-25 1996-04-25 Device for controlling local bus KR100362061B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960012934A KR100362061B1 (en) 1996-04-25 1996-04-25 Device for controlling local bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960012934A KR100362061B1 (en) 1996-04-25 1996-04-25 Device for controlling local bus

Publications (2)

Publication Number Publication Date
KR970071310A true KR970071310A (en) 1997-11-07
KR100362061B1 KR100362061B1 (en) 2003-03-03

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Application Number Title Priority Date Filing Date
KR1019960012934A KR100362061B1 (en) 1996-04-25 1996-04-25 Device for controlling local bus

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100572945B1 (en) * 1998-02-04 2006-04-24 텍사스 인스트루먼츠 인코포레이티드 Digital signal processor with efficiently connectable hardware co-processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100528443B1 (en) * 1997-09-23 2006-01-27 삼성전자주식회사 Data transmission circuit of digital signal processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920002665B1 (en) * 1989-12-26 1992-03-31 재단법인 한국전자통신연구소 A method for generating local bus cycle in multi processing system
KR0123974Y1 (en) * 1992-12-30 1998-09-15 정장호 The transmitting circuits in a vme bus
KR950009460A (en) * 1993-09-28 1995-04-24 김연수 Module removal and mounting device of computer system
JPH0836543A (en) * 1994-07-22 1996-02-06 Sharp Corp Method and device for detecting slave board
JPH0877101A (en) * 1994-09-08 1996-03-22 Mitsubishi Electric Corp Bus controller and signal processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100572945B1 (en) * 1998-02-04 2006-04-24 텍사스 인스트루먼츠 인코포레이티드 Digital signal processor with efficiently connectable hardware co-processor

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