JPS5622157A - Process system multiplexing system - Google Patents

Process system multiplexing system

Info

Publication number
JPS5622157A
JPS5622157A JP9821079A JP9821079A JPS5622157A JP S5622157 A JPS5622157 A JP S5622157A JP 9821079 A JP9821079 A JP 9821079A JP 9821079 A JP9821079 A JP 9821079A JP S5622157 A JPS5622157 A JP S5622157A
Authority
JP
Japan
Prior art keywords
memory
register
written
data
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9821079A
Other languages
Japanese (ja)
Inventor
Shuji Yoshida
Kenji Morosawa
Masahiro Hata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9821079A priority Critical patent/JPS5622157A/en
Publication of JPS5622157A publication Critical patent/JPS5622157A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To eliminate the procedure for the transmission of data between the process system and at the same time secure an independent unit constitution for each system, by providing the principal and vice bus controllers between the systems.
CONSTITUTION: Process system A consisting of CPU1 and memory 2 is connected to process system B comprising CPU4 and memory 5 via principal bus controller BCCM11-1 and vice bus controller BCCS12-1. At the same time, BCCS11-2 is connected to BCCM12-2 via line wires 13 and 14 each. In case the communication is given to system B from system A, the address of memory 5 is written into memory address register 21 of BCCS12-1 from CPU1. And the data is written into output buffer register 22. At the same time, the data of register 22 is written into memory 5 under the control of direct memory access control circuit 23. In case the communication is received at system A from system B, the data given from memory 5 is written into input buffer register 34 by the reading command given from command register 33. And CPU1 gives access to register 34 to read out the contents.
COPYRIGHT: (C)1981,JPO&Japio
JP9821079A 1979-07-31 1979-07-31 Process system multiplexing system Pending JPS5622157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9821079A JPS5622157A (en) 1979-07-31 1979-07-31 Process system multiplexing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9821079A JPS5622157A (en) 1979-07-31 1979-07-31 Process system multiplexing system

Publications (1)

Publication Number Publication Date
JPS5622157A true JPS5622157A (en) 1981-03-02

Family

ID=14213611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9821079A Pending JPS5622157A (en) 1979-07-31 1979-07-31 Process system multiplexing system

Country Status (1)

Country Link
JP (1) JPS5622157A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5962960A (en) * 1982-10-02 1984-04-10 Horiba Ltd Data transfer circuit of computer
JP2004508635A (en) * 2000-09-06 2004-03-18 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Communication system between processors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5962960A (en) * 1982-10-02 1984-04-10 Horiba Ltd Data transfer circuit of computer
JP2004508635A (en) * 2000-09-06 2004-03-18 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Communication system between processors
JP4915631B2 (en) * 2000-09-06 2012-04-11 エスティー‐エリクソン、ソシエテ、アノニム Interprocessor communication system

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