JPS5764835A - Direct memory access system of microprocessor - Google Patents
Direct memory access system of microprocessorInfo
- Publication number
- JPS5764835A JPS5764835A JP55140951A JP14095180A JPS5764835A JP S5764835 A JPS5764835 A JP S5764835A JP 55140951 A JP55140951 A JP 55140951A JP 14095180 A JP14095180 A JP 14095180A JP S5764835 A JPS5764835 A JP S5764835A
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- microprocessor
- memory access
- direct memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Microcomputers (AREA)
Abstract
PURPOSE:To simplify the hardware and to increase the data transfer capacity, by fixing the number of transfer words of a direct memory access and securing the corresponding between the direction of data transfer and the hardware. CONSTITUTION:A direct memory access device 3 is provided to each terminal device of a microprocessor controller. When a data is transmitted from a microprocessor 1, the address setting of a transmitting memory address register 31 is started to read the produced data out of a memory 2 by a fixed number of words through a control circuit 32. This data is transmitted to a terminal device through a bus bar 8 via a terminal device interface circuit 35. When the data is received, an area is secured in the memory 2. At the same time, an address is set to an address register 33, and the received data is written into the memory 2 by a fixed number of words through a control circuit 34 by an instruction given from the circuit 35.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55140951A JPS5764835A (en) | 1980-10-07 | 1980-10-07 | Direct memory access system of microprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55140951A JPS5764835A (en) | 1980-10-07 | 1980-10-07 | Direct memory access system of microprocessor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5764835A true JPS5764835A (en) | 1982-04-20 |
Family
ID=15280600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55140951A Pending JPS5764835A (en) | 1980-10-07 | 1980-10-07 | Direct memory access system of microprocessor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5764835A (en) |
-
1980
- 1980-10-07 JP JP55140951A patent/JPS5764835A/en active Pending
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