JPS56116138A - Input and output controller - Google Patents

Input and output controller

Info

Publication number
JPS56116138A
JPS56116138A JP1838980A JP1838980A JPS56116138A JP S56116138 A JPS56116138 A JP S56116138A JP 1838980 A JP1838980 A JP 1838980A JP 1838980 A JP1838980 A JP 1838980A JP S56116138 A JPS56116138 A JP S56116138A
Authority
JP
Japan
Prior art keywords
memory
circuit
read
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1838980A
Other languages
Japanese (ja)
Inventor
Kenichi Onishi
Minoru Nagao
Makoto Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP1838980A priority Critical patent/JPS56116138A/en
Publication of JPS56116138A publication Critical patent/JPS56116138A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To realize a direct transfer of data between an I/O circuit and a memory, by sending the output of a decoder to the I/O circuit and at the same time sending a read or write instruction to the memory. CONSTITUTION:In case the address designation signal of the memory 2 delivered from the CPU1 designates the address range of the write-only or read-only area of the memory 2 decided previously, the address decoder 6 delivers the input/output control signal according to the exclusive area. When the read or write instruction plus the memory request signal are delivered from the CPU1, the output of the decoder 6 is sent to the I/O circuit 20 in the form of the data input/output signal. At the same time, the read or write instruction is sent to the memory 2 via the gate circuit 7. In such way, a direct transfer of data is possible between the circuit 20 and the memory 2.
JP1838980A 1980-02-15 1980-02-15 Input and output controller Pending JPS56116138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1838980A JPS56116138A (en) 1980-02-15 1980-02-15 Input and output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1838980A JPS56116138A (en) 1980-02-15 1980-02-15 Input and output controller

Publications (1)

Publication Number Publication Date
JPS56116138A true JPS56116138A (en) 1981-09-11

Family

ID=11970348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1838980A Pending JPS56116138A (en) 1980-02-15 1980-02-15 Input and output controller

Country Status (1)

Country Link
JP (1) JPS56116138A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097458A (en) * 1983-10-18 1985-05-31 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data transfer unit
JPS629456A (en) * 1985-07-01 1987-01-17 ハネウエル・インコーポレーテッド Data transfer unit
JPH03129450A (en) * 1989-07-21 1991-06-03 Matsushita Electric Ind Co Ltd Method and device for data transfer
WO1991011811A1 (en) * 1990-01-26 1991-08-08 Nintendo Co., Ltd. Digital sound source device and external memory cartridge used therefor
JPH0736824A (en) * 1993-07-20 1995-02-07 Kanoopusu Kk Data transfer system and method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097458A (en) * 1983-10-18 1985-05-31 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data transfer unit
JPH0316660B2 (en) * 1983-10-18 1991-03-06 Intaanashonaru Bijinesu Mashiinzu Corp
JPS629456A (en) * 1985-07-01 1987-01-17 ハネウエル・インコーポレーテッド Data transfer unit
JPH03129450A (en) * 1989-07-21 1991-06-03 Matsushita Electric Ind Co Ltd Method and device for data transfer
WO1991011811A1 (en) * 1990-01-26 1991-08-08 Nintendo Co., Ltd. Digital sound source device and external memory cartridge used therefor
GB2249889A (en) * 1990-01-26 1992-05-20 Nintendo Co Ltd Digital sound source device and external memory cartridge used therefor
GB2249889B (en) * 1990-01-26 1993-12-15 Nintendo Co Ltd Digital sound source apparatus and external memory cartridge used therefor
US5317714A (en) * 1990-01-26 1994-05-31 Nintendo Co., Ltd. Digital sound source apparatus and external memory cartridge used therefor
JPH0736824A (en) * 1993-07-20 1995-02-07 Kanoopusu Kk Data transfer system and method thereof

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