JPS54128226A - Random access memory - Google Patents

Random access memory

Info

Publication number
JPS54128226A
JPS54128226A JP3552178A JP3552178A JPS54128226A JP S54128226 A JPS54128226 A JP S54128226A JP 3552178 A JP3552178 A JP 3552178A JP 3552178 A JP3552178 A JP 3552178A JP S54128226 A JPS54128226 A JP S54128226A
Authority
JP
Japan
Prior art keywords
address
data
input
information
random access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3552178A
Other languages
Japanese (ja)
Inventor
Katsunori Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3552178A priority Critical patent/JPS54128226A/en
Publication of JPS54128226A publication Critical patent/JPS54128226A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To reduce the number of both the information line and the input/output terminal by supplying and delivering the address information and the write/read information in the time-division system. CONSTITUTION:Multiplexer 2 is provided at the address data input/output part of random access memory (RAM) 1, the the address signal line and the data signal line are used in common inside RAM1. Multiplexer 2 consists of transmission gate MISFET (Q1-Q5) which uses the common information line or input/output terminal in time division. In other words, the allotment in terms of time is given to the address and the data via control signal D/A which prescribes the input/output control for the address and the data, and the distinction is given between writing data (din) and reading data (dout) by the write/read order (r/w).
JP3552178A 1978-03-29 1978-03-29 Random access memory Pending JPS54128226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3552178A JPS54128226A (en) 1978-03-29 1978-03-29 Random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3552178A JPS54128226A (en) 1978-03-29 1978-03-29 Random access memory

Publications (1)

Publication Number Publication Date
JPS54128226A true JPS54128226A (en) 1979-10-04

Family

ID=12444043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3552178A Pending JPS54128226A (en) 1978-03-29 1978-03-29 Random access memory

Country Status (1)

Country Link
JP (1) JPS54128226A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853082A (en) * 1981-09-24 1983-03-29 Hitachi Ltd Static type ram
EP0198429A2 (en) * 1985-04-10 1986-10-22 Nec Corporation Word length selectable memory
WO1994028550A1 (en) * 1993-06-02 1994-12-08 Rambus, Inc. Dynamic random access memory system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853082A (en) * 1981-09-24 1983-03-29 Hitachi Ltd Static type ram
JPH0449196B2 (en) * 1981-09-24 1992-08-10 Hitachi Seisakusho Kk
EP0198429A2 (en) * 1985-04-10 1986-10-22 Nec Corporation Word length selectable memory
WO1994028550A1 (en) * 1993-06-02 1994-12-08 Rambus, Inc. Dynamic random access memory system
US5430676A (en) * 1993-06-02 1995-07-04 Rambus, Inc. Dynamic random access memory system
US5434817A (en) * 1993-06-02 1995-07-18 Rambus, Incorporated Dynamic random access memory system
US5511024A (en) * 1993-06-02 1996-04-23 Rambus, Inc. Dynamic random access memory system

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