JPS5750378A - Control system of data processor - Google Patents

Control system of data processor

Info

Publication number
JPS5750378A
JPS5750378A JP55123886A JP12388680A JPS5750378A JP S5750378 A JPS5750378 A JP S5750378A JP 55123886 A JP55123886 A JP 55123886A JP 12388680 A JP12388680 A JP 12388680A JP S5750378 A JPS5750378 A JP S5750378A
Authority
JP
Japan
Prior art keywords
processor
transfer
block
data
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55123886A
Other languages
Japanese (ja)
Inventor
Kunio Nakase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55123886A priority Critical patent/JPS5750378A/en
Publication of JPS5750378A publication Critical patent/JPS5750378A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce the overall data processing time, by properly providing an idle time to a buffer memory device during the transfer period of block. CONSTITUTION:The data used by a processor 1 is read out of a main storage device 2 and stored temporarily in a buffer memory device 4. In addition to the device 4, a block transfer circuit 3 is provided for the processor 1 to transmit the transfer indication information including an address to the device 2. When the data required for the processor 1 is not stored in the device 4, a data block is transferred to the device 4 from the device 2. In this case, the transfer is carried out as divided in plural times and provided with time intervals. In these time intervals, an access is given to the device 4 from the processor 1 through a control.
JP55123886A 1980-09-05 1980-09-05 Control system of data processor Pending JPS5750378A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55123886A JPS5750378A (en) 1980-09-05 1980-09-05 Control system of data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55123886A JPS5750378A (en) 1980-09-05 1980-09-05 Control system of data processor

Publications (1)

Publication Number Publication Date
JPS5750378A true JPS5750378A (en) 1982-03-24

Family

ID=14871791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55123886A Pending JPS5750378A (en) 1980-09-05 1980-09-05 Control system of data processor

Country Status (1)

Country Link
JP (1) JPS5750378A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195346A (en) * 1987-09-21 1989-04-13 Motorola Inc Bus master
JPH0195345A (en) * 1987-09-21 1989-04-13 Motorola Inc Bus master

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195346A (en) * 1987-09-21 1989-04-13 Motorola Inc Bus master
JPH0195345A (en) * 1987-09-21 1989-04-13 Motorola Inc Bus master

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